Transistor Isolation Below Source and Drain to Block Subfin Leakage
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Solution Overview
Problem
FinFET devices experience parasitic leakage between the source and drain regions, which is challenging to control, especially in III-V transistors where traditional doping methods are ineffective due to rapid dopant diffusion.
Innovation Solution
The implementation of an isolation structure made of insulator material below the source and drain regions in tri-gate and gate-all-around transistor configurations, which blocks parasitic leakage by extending along and contacting the bottom surface of the source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional doping methods are used in III-V transistors, then the manufacturing process is simple, but parasitic leakage between source and drain regions cannot be controlled due to rapid dopant diffusion
Solution Approach 1:
The patent extracts the doping function entirely from the manufacturing process and replaces it with a structural solution. Instead of attempting to control dopant diffusion, the invention removes the need for doping by using an undoped semiconductor body with a specifically engineered isolation structure that provides electrical isolation through physical geometry and material properties rather than chemical modification
Solution Approach 2:
The isolation structure acts as an intermediary element between the source and drain regions. This structure, comprising insulator material positioned below the source and drain regions and extending along their bottom surfaces, mediates the electrical interaction between these regions by providing a physical barrier that prevents parasitic leakage without requiring direct modification of the source or drain regions themselves
2Reliability
If no isolation structure is used below source and drain regions, then the device structure is simple, but parasitic subfin leakage occurs in FinFET devices
Solution Approach 1:
The patent addresses the leakage problem by moving the isolation function to a different spatial dimension. Instead of placing isolation material laterally between source and drain regions (which would increase planar complexity), the invention positions insulator material vertically below the source and drain regions, utilizing the depth dimension to achieve electrical isolation while maintaining a relatively simple planar device footprint
Solution Approach 2:
The isolation structure exhibits asymmetric positioning relative to the source and drain regions. The insulator material is strategically placed only below specific regions (source and drain) rather than uniformly throughout the device, creating an asymmetric configuration that targets parasitic leakage paths selectively without requiring symmetric complexity throughout the entire device structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces or eliminates parasitic subfin leakage, enhancing the performance of FinFET devices and improving the scalability of III-V transistors.
Implementation Method 1
an isolation structure made of insulator material below the source and drain regions... which blocks parasitic leakage by extending along and contacting the bottom surface of the source and drain regions
Data Source
AI summary
A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).