SRAM Cell Layout With Backside Word Lines for Lower RC Loading
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, issues such as cross talk and wiring resistance in memory circuits, particularly in SRAM devices, lead to RC delay and coupling noises, which slow down cell speed and limit scaling ratios.
Innovation Solution
The solution involves an integrated circuit design where word lines and high-voltage power lines are formed on the back side of memory cells, while bit lines and low-voltage power lines are formed on the front side, with edge cells having word line tap structures to connect front and back side word lines, thereby reducing RC loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If routing conductors (Word lines and Bit lines) are used in memory circuits, then digital data storage and transmission are enabled, but RC delay and coupling noise are generated which slow down cell speed and limit scaling ratio
Solution Approach 1:
The patent introduces a third dimension by forming word lines on the back side of the substrate and bit lines on the front side, creating a 3D interconnect architecture. This vertical separation of different signal types eliminates RC delay and coupling noise issues in planar designs, enabling faster cell operation and improved scaling
Solution Approach 2:
The patent segments the routing conductors into functionally separate layers: word lines are routed on the back side while bit lines are routed on the front side. This segmentation isolates different signal paths, preventing cross-talk and reducing overall RC loading in the memory circuit
2Area of stationary object
If IC scaling is pursued to reduce size, then device density increases, but wiring resistance and cross talk effects worsen affecting performance
Solution Approach 1:
By transitioning from 2D planar routing to 3D vertical routing with front-side and back-side conductor layers, the patent reduces the area required for interconnects while maintaining signal integrity. This enables continued scaling without proportionally increasing wiring resistance and cross-talk effects
Solution Approach 2:
The patent introduces an intermediary substrate structure that physically separates word lines and bit lines into different spatial domains (back side vs. front side). This intermediary architecture acts as a barrier against electromagnetic coupling, reducing cross-talk while enabling higher density integration
Data Source
AI summary
Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells having the word lines and high-voltage power lines positioned on one side of the transistors and the bit lines and low voltage power lines positioned on the other side of the transistor. The memory cells according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell.