Gate Contact Plug Structure for Fine-Pattern MOSFET Integration
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices poses challenges in manufacturing devices with fine patterns and narrow separation distances, while also requiring improvements in the operating characteristics of planar metal oxide semiconductor FETs.
Innovation Solution
A semiconductor device design that includes an active region on a substrate with an impurity region, a gate structure intersecting the active region, a spacer structure on both sides of the gate electrode, and a capping layer protecting the gate electrode and spacer structure. The capping layer consists of a lower and upper capping layer, with the second contact plug penetrating through and having a convex sidewall that curves into the upper capping layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to meet high performance demand, then device functionality and speed improve, but manufacturing precision requirements worsen due to fine patterns and narrow separation distances
Solution Approach 1:
The gate structure is segmented into multiple components including gate electrode, lower capping layer, upper capping layer, and spacer structures. This segmentation allows each component to be optimized independently for both performance and manufacturability, addressing the contradiction between integration density and manufacturing precision
Solution Approach 2:
Different regions of the device structure are assigned different material properties and geometries. The capping layers have different etch selectivities, the spacer structures have specific width profiles, and the gate electrode has optimized dimensions. This local quality approach enables precise control over manufacturing processes while maintaining high device performance
2Productivity
If planar metal oxide semiconductor FET size is reduced for high integration, then device density improves, but operating characteristics worsen due to size reduction limitations
Solution Approach 1:
The invention transitions from planar FET architecture to a three-dimensional gate structure with vertical capping layers and spacer structures. This dimensional change allows the device to achieve high integration density through vertical stacking while maintaining improved operating characteristics through the enhanced gate control provided by the multi-layer structure
Solution Approach 2:
The gate structure employs composite materials including metal oxide semiconductor channel layers, conductive gate electrode materials, and dielectric capping layer materials with different etch selectivities. This composite approach enables simultaneous optimization of electrical performance and manufacturing processability, resolving the contradiction between density and reliability
Data Source
AI summary
A semiconductor device includes an active region extending on a substrate in a first direction, a gate structure including a gate electrode extending on the substrate in a second direction and traversing the active region, a spacer structure extending on opposing sidewalls of the gate electrode in the second direction, and a capping layer on the gate electrode and the spacer structure, a source/drain region on the active region adjacent the gate structure, and a first contact plug connected to the source/drain region and a second contact plug connected to the gate structure. The capping layer includes a lower capping layer and an upper capping layer on the lower capping layer, and the second contact plug penetrates through the capping layer, is connected to the gate electrode and includes a convex sidewall penetrating into the upper capping layer.