Backside Probe Access for Gate-All-Around Transistor Debug
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Solution Overview
Problem
Current techniques for fault isolation and failure analysis in integrated circuits are limited in accessing advanced architectures, particularly in the context of increasing demands for faster product ramps, and are invasive, making them less effective for debugging complex designs.
Innovation Solution
The use of focused ion beam (FIB) machining and ion beam induced deposition (IBID) to directly access and modify gate-all-around transistor structures from the back side, allowing for the formation of edit wires and probe points for testing and circuit editing, enabling more efficient and non-invasive debugging and validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional probing techniques are used to access transistor nodes, then fault isolation and failure analysis can be performed, but the access is invasive and limited for advanced architectures
Solution Approach 1:
The patent accesses transistor nodes from the back side of the substrate rather than through the front side, utilizing the z-dimension (vertical axis) to bypass traditional probing limitations. This dimensional approach allows non-invasive access to gate-all-around transistor nodes without disrupting front-side circuitry or requiring substrate penetration from the conventional side.
Solution Approach 2:
The patent introduces back-side access probe points as intermediary structures that facilitate electrical connection to transistor nodes without direct mechanical probing of the devices themselves. These probe points serve as mediators between the testing equipment and the sensitive transistor nodes, enabling fault isolation while minimizing physical intrusion and potential damage.
2Difficulty of detecting and measuring
If mechanical probing through silicon substrate is used, then circuit level analysis can be performed, but the technique is limited for advanced architectures and slower
Solution Approach 1:
The patent incorporates back-side access probe points during the semiconductor manufacturing process itself, before the product is fully assembled and shipped. This preliminary action ensures that test access structures are already in place, eliminating the need for time-consuming post-manufacturing modifications or complex probing setups, thereby accelerating product validation and ramp speed.
Solution Approach 2:
The patent replaces mechanical probing through the substrate with electrical connection through back-side probe points. Instead of physically penetrating the silicon substrate with mechanical probes, the system uses pre-formed conductive pathways and probe points that provide electrical access without mechanical intrusion, significantly reducing setup time and enabling faster circuit level analysis.
3Adaptability or versatility
If front end metal interconnect layers are used for circuit editing, then design validation can be performed, but access to advanced architectures is limited
Solution Approach 1:
The patent inverts the traditional approach to circuit editing by accessing and modifying circuits from the back side rather than the front side. Instead of routing edit wires through front-end metal interconnect layers, the system uses back-side probe points to directly access transistor nodes, simplifying the editing process for advanced architectures like gate-all-around transistors where front-side access is highly complex.
Solution Approach 2:
The patent segments the testing and validation functions by separating probe access from front-side interconnect structures. Back-side probe points provide dedicated access pathways for specific transistor nodes, allowing independent testing and validation without interfering with front-side signal routing. This segmentation simplifies the overall system complexity while enhancing design validation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides improved access to transistor nodes with reduced machining geometries and invasiveness, facilitating faster product validation, reduced production cycles, and increased yields by enabling efficient testing and modification of gate-all-around transistor circuits.
Implementation Method 1
The use of focused ion beam (FIB) machining and ion beam induced deposition (IBID) to directly access and modify gate-all-around transistor structures from the back side
Implementation Method 2
The use of focused ion beam (FIB) machining and ion beam induced deposition (IBID) to directly access and modify gate-all-around transistor structures from the back side
Data Source
AI summary
Techniques and structures are disclosed related to coupling to gate-all-around transistors for test and/or debug of an integrated circuit. The gate-all-around transistors, which may also be referred to as 3D stacked transistors or ribbon-FET transistors are contacted directly from the back side or they are contacted using a dedicated probe point on the back side of the gate-all-around transistors. Such contact may be made to probe the devices and/or to provide edit wires to modify the integrated circuit.