Backside Redistribution Layer Via Interconnect
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Solution Overview
Problem
As IC devices scale to smaller sizes, existing technologies face challenges in further size scaling of the die or package substrate and efficiently routing electrical pathways to accommodate input/output (I/O) signal, power, or ground voltage requirements.
Innovation Solution
The implementation of a semiconductor substrate with a redistribution layer on its backside, utilizing vias to couple the front and back surfaces, allowing for the delivery of I/O signals, power, and ground voltage through these vias, and integrating with a package substrate or printed circuit board using die attach materials and wire bonds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If IC devices are scaled to smaller sizes, then device density and integration are improved, but routing electrical pathways and accommodating I/O signal requirements become more difficult
Solution Approach 1:
The patent introduces a third dimension by forming vias through the semiconductor substrate to create a redistribution layer on the backside. This vertical dimension allows I/O signals to be routed through the substrate thickness, effectively adding a new layer of interconnection that bypasses the planar routing constraints on the front surface, thereby reducing routing complexity while maintaining high device density.
Solution Approach 2:
The patent segments the interconnection function by separating I/O signal routing from the front surface circuitry. The redistribution layer on the backside handles I/O signals, power, and ground connections, while the front surface focuses on active devices and internal circuitry. This functional segmentation simplifies the overall routing complexity by distributing interconnection tasks across different surfaces and layers.
2Area of moving object
If die size is reduced, then package size and integration density are improved, but the number of I/O signal connections required increases
Solution Approach 1:
By utilizing the vertical dimension through via holes, the patent enables multiple I/O connections to be established through a compact substrate area. The backside redistribution layer can accommodate multiple connection points without increasing the die footprint, as connections are distributed through the thickness of the substrate rather than competing for surface area.
Solution Approach 2:
The backside redistribution layer serves multiple functions simultaneously: it provides I/O signal connections, power delivery, and ground references through the same via structure. This multi-functionality reduces the total number of separate connection elements needed, allowing compact die sizes while maintaining comprehensive electrical connectivity.
3Power
If power and ground voltage delivery is improved, then device performance is enhanced, but the complexity of electrical pathway routing increases
Solution Approach 1:
The patent routes power and ground pathways through the vertical dimension using vias that penetrate the substrate. This three-dimensional power distribution network allows multiple power and ground connections to be established without increasing planar routing complexity, as the pathways utilize the substrate thickness rather than competing for surface routing space.
Solution Approach 2:
The patent merges power, ground, and I/O signal routing into a unified backside redistribution layer structure. By combining these electrical pathways in a single integrated layer on the backside, the patent simplifies the overall electrical architecture while maintaining enhanced power and ground delivery capabilities to all devices.
Data Source
AI summary
Embodiments of the present invention provide an apparatus that includes a semiconductor substrate comprising a first surface having one or more integrated circuit devices formed thereon and a second surface opposite the first surface, wherein one or more vias are formed through the semiconductor substrate to couple the first surface with the second surface. The apparatus may further include a redistribution layer coupled with the second surface of the semiconductor substrate, wherein the one or more vias couple the redistribution layer with the first surface of the semiconductor substrate. Other embodiments including, for example, associated packages and methods may be described and/or claimed.