Backside Redistribution Layer for Semiconductor Wafer Interconnect
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Solution Overview
Problem
Current semiconductor packaging techniques using through-hole vias (THVs) around saw streets limit signal routing options and density, making it difficult to achieve high density and flexible interconnects required for modern semiconductor devices.
Innovation Solution
The method involves forming conductive vias and layers around the semiconductor die, with a portion of the conductive layer electrically connected to the vias and another portion isolated, along with the use of backside redistribution layers for increased interconnect flexibility and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If through-hole vias are used around saw streets for interconnect, then device integration is achieved, but signal routing options and density are limited
Solution Approach 1:
The interconnect structure is segmented into multiple functional layers: through-hole vias for vertical inter-die connection, backside redistribution layers for signal routing within a die, and frontside conductive layers for additional routing options. This segmentation allows signals to be routed through different paths and layers, dramatically increasing routing flexibility without requiring a complete redesign of the through-hole via structure.
Solution Approach 2:
The invention adds the backside of the die as another dimension for signal routing. By placing redistribution layers on the backside of the substrate, signals can be routed in a planar fashion on the backside before being connected to frontside contacts or to other dies through through-hole vias. This dimensional addition transforms the routing architecture from purely vertical (through-hole) to a combination of planar (backside RDL) and vertical (THV) paths.
2Productivity
If through-hole vias are used for inter-die connection, then three-dimensional interconnect is achieved, but signal routing density is reduced
Solution Approach 1:
The backside redistribution layer acts as an intermediary between the through-hole vias and the frontside contact pads. Instead of requiring long, complex routing paths through multiple through-hole vias, signals can be distributed locally on the backside RDL and then connected to through-hole vias at optimal locations. This intermediary layer reduces the effective interconnect length and increases routing density by providing local signal distribution points.
3Adaptability or versatility
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but high density and flexible interconnect capability are difficult to achieve
Solution Approach 1:
The backside redistribution layers and frontside conductive layers are formed on the substrate before the final packaging and stacking operations. This preliminary formation of the interconnect architecture allows subsequent die stacking and through-hole via formation to proceed using standard processes, while the pre-configured routing layers provide the flexibility and density required for high-performance applications. The complex routing structure is prepared in advance rather than attempting to create it during final assembly.
Data Source
AI summary
A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and through-hole vias (THV) provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die.