Backside Resistor Structure for Precision IC Routing Relief
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Solution Overview
Problem
As IC devices miniaturize, the available area for forming contacts and interconnects decreases, leading to increased routing complexity, parasitic resistance, and capacitance, which negatively impact manufacturing costs and performance.
Innovation Solution
Implementing high-precision backside resistors by fabricating them between frontside and backside metal layers, utilizing backside contacts and vias to connect to frontside structures, allowing for no change to the existing frontside BEOL process and freeing up frontside routing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If IC devices are miniaturized to advance computing power, then computing power increases, but routing complexity and parasitic resistance increase
Solution Approach 1:
The patent moves the resistor implementation from the traditional frontside interconnect layer to the backside of the substrate. This dimensional relocation allows resistors to be formed in a previously underutilized space, separating them from the dense frontside routing and reducing routing complexity without impacting computing power.
Solution Approach 2:
The patent divides the substrate into frontside and backside regions with distinct functions. The frontside handles active components and interconnects, while the backside is dedicated to passive components like resistors. This segmentation reduces the complexity of frontside routing by relocating resistor implementations to the backside.
2Length of moving object
If IC devices are miniaturized, then device size decreases, but parasitic resistance increases
Solution Approach 1:
By relocating resistors to the backside of the substrate, the patent creates longer, more controlled resistor paths that are physically separated from the frontside interconnects. This dimensional separation reduces the parasitic resistance impact on frontside signaling while maintaining compact device dimensions.
Solution Approach 2:
The substrate itself acts as an intermediary medium, with resistors formed in the backside region serving as mediators between the frontside circuits and the ground plane. This intermediary positioning allows for better control of parasitic effects while maintaining signal integrity.
3Adaptability or versatility
If more contacts and interconnects are formed on the frontside, then connectivity increases, but available area decreases
Solution Approach 1:
The patent utilizes the backside of the substrate as an additional dimensional space for implementing passive components. This allows frontside area to be fully dedicated to active components and interconnects, maximizing connectivity without sacrificing available area, as resistors are now formed in the backside region.
Solution Approach 2:
The patent segments the substrate into frontside and backside functional regions. The frontside is optimized for high-density interconnects and active components, while the backside accommodates passive components like resistors. This segmentation enables maximum connectivity on the frontside without compromising available area.
4Ease of manufacture
If frontside routing resources are used for resistors, then resistor implementation is simple, but routing resources are consumed
Solution Approach 1:
The patent relocates resistor formation to the backside of the substrate, utilizing the previously underutilized backside region. This dimensional relocation maintains the simplicity of resistor implementation through standard thin-film deposition processes while freeing up frontside routing resources for signal interconnects.
Solution Approach 2:
The patent extracts the resistor implementation from the frontside routing layer and places it in the backside region. This extraction eliminates the conflict between resistor area requirements and routing resource availability, as resistors are now formed in a separate spatial domain without consuming frontside routing resources.
Data Source
AI summary
A high-precision backside resistor and method for making the same are disclosed. In an aspect, a backside resistor structure disposed between a frontside level-zero metal (FM0) layer and a backside level-zero metal (BM0) layer comprises a first terminal electrically coupled to a first frontside structure through a first conductive path comprising at least a first backside contact (BSC), and a second terminal electrically coupled to a second frontside structure through a second conductive path comprising at least a second BSC.