Backside Self-Aligned Source/Drain Contact for Dense Nanosheet FETs
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Solution Overview
Problem
The semiconductor industry faces challenges with advanced technologies like 7 nm, 5 nm, and 3 nm ICs due to contact to gate bridging, alignment margins, and increased complexity in processing and manufacturing, particularly with multi-gate transistors and backside power rails, which suffer from issues such as shorting, leakage, routing resistance, and reduced packing density.
Innovation Solution
A semiconductor structure with backside power rails and self-aligned vias is developed, where backside vias are electrically connected to device features like the source of a field-effect transistor, and an interconnect structure on the frontside distributes power rails, reducing overlay shifting and shorting, and providing more space for metal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional backside power rails are used in advanced technologies, then power distribution is provided, but shorting and leakage issues occur due to alignment margins and contact to gate bridging
Solution Approach 1:
The patent moves the power rail connection from the frontside to the backside of the semiconductor device, utilizing the third dimension (vertical stacking) to resolve the alignment conflict. By forming backside vias that connect to source/drain regions through the substrate, the power distribution network operates in a different spatial plane, eliminating the overlay shifting and shorting issues that plague conventional frontside power rails in advanced nodes
Solution Approach 2:
The patent segments the power distribution network into frontside and backside components. Frontside interconnects handle gate and drain connections, while backside interconnects handle source power distribution. This segmentation allows independent optimization of each network, with backside vias specifically sized and positioned to avoid gate bridging while maintaining source contact
2Productivity
If device sizes are scaled down to increase packing density, then more devices fit per chip area, but alignment margins are reduced causing shorting and leakage
Solution Approach 1:
By transitioning to three-dimensional integrated circuits with backside connections, the patent enables tighter frontside pitch without compromising alignment margins. The backside vias provide a separate connection path that does not compete for the same lateral alignment tolerance, allowing continued scaling while maintaining manufacturing yield
Solution Approach 2:
The substrate acts as an intermediary element that enables backside via formation. By routing connections through the substrate thickness rather than laterally across the chip, the system gains an additional degree of freedom in path routing, allowing source power connections to be made without interfering with gate alignment
3Quantity of substance
If frontside interconnect space is used for power rails, then power distribution is achieved, but space for metal routing is reduced
Solution Approach 1:
The patent divides the interconnect function between frontside and backside of the device. Frontside interconnect layers are dedicated to signal routing and gate connections, while backside interconnect layers handle power distribution. This functional segmentation frees up frontside metal routing space while ensuring adequate power rail provision through the backside network
Solution Approach 2:
The patent utilizes the vertical dimension by forming power rails and vias on the backside of the substrate. This three-dimensional power distribution approach allows power delivery without consuming lateral planar space, effectively doubling the available routing area on the frontside while maintaining robust power supply through the substrate thickness
Data Source
AI summary
A semiconductor structure includes nanostructures vertically stacked over a fin-shaped base, an isolation structure disposed on sidewalls of the fin-shaped base, a gate structure wrapping around at least one of the nanostructures, first and second source/drain epitaxial features abutting and sandwiching the nanostructures, a frontside source/drain contact over and in electrical coupling with the first source/drain epitaxial feature, a semiconductor layer under the first source/drain epitaxial feature and interfacing with the isolation structure, a backside source/drain contact under and in electrical coupling with the second source/drain epitaxial feature, a backside spacer layer interposing the backside source/drain contact and a sidewall of the fin-shaped base, the backside spacer layer interfacing with the isolation structure, and a backside interconnect structure under the backside source/drain contact and in electrical coupling with the backside source/drain contact.