Backside TSV Interconnect Structure for Higher-Density 3D ICs
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing circuit density due to physical constraints in two-dimensional ICs, prompting the need for three-dimensional ICs with through-substrate vias (TSVs) that require complex designs and larger carrier substrates for wire bonding.
Innovation Solution
A method for forming semiconductor devices with backside interconnect structures on TSVs, involving thinning the substrate to expose TSVs, forming isolation films, depositing conductive layers, and patterning them to create concave or convex surfaces for efficient electrical connections, allowing for flexible placement and higher integration density without the need for large carrier substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional IC layout is used to increase integration density, then more components can be integrated into a given area, but physical limits are reached due to minimum feature size constraints
Solution Approach 1:
The patent transitions from two-dimensional IC layout to three-dimensional stacked die architecture by forming through-substrate vias (TSVs) that extend vertically through the substrate. This enables stacking multiple dies in the vertical dimension, thereby increasing integration density without being constrained by minimum feature size limits in the planar dimension.
2Quantity of substance
If through-substrate vias are formed to enable 3D IC stacking, then integration density increases, but complex designs and larger carrier substrates are required for wire bonding
Solution Approach 1:
The patent extracts the wire bonding function from the carrier substrate and implements direct electrical connections through the substrate using TSVs. By removing the carrier substrate and wire bonding complexity, the design achieves simpler 3D IC stacking with direct via connections between dies.
3Reliability
If carrier substrate is used for wire bonding in 3D IC formation, then electrical connections between dies can be established, but the carrier substrate must be larger than the dies
Solution Approach 1:
The patent moves electrical connections from the planar dimension (carrier substrate surface) to the vertical dimension (through-substrate vias). This enables direct vertical connections between stacked dies without requiring a large carrier substrate, reducing the overall package area while maintaining reliable electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with enhanced integration density and flexible electrical connections, overcoming the limitations of two-dimensional ICs and reducing the size requirements for carrier substrates, thereby improving the efficiency and complexity of 3D IC formation.
Implementation Method 1
the substrate is thinned to expose the through-substrate via
Implementation Method 2
a conductive layer is deposited on the isolation film and the through-substrate via
Data Source
AI summary
A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.