Backside Via Layout for Nanosheet Power Rail Connections
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Solution Overview
Problem
As semiconductor devices scale down, nanosheet transistors interfere with each other, and forming connections to a backside power network becomes increasingly difficult.
Innovation Solution
A backside via is formed between nanodevices to connect source/drain contacts to a backside power rail, reducing the risk of tip-to-tip shorts and simplifying patterning by extending from the backside of the nanodevice.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet transistors are scaled down and placed closer together, then device density is improved, but device interference increases and connection formation becomes more difficult
Solution Approach 1:
The patent transitions the connection approach from the frontside (2D plane) to the backside (3D dimension) of the nanodevices. By forming via holes through the substrate from the backside, the connection path moves to a different spatial dimension, allowing connections to be made without interfering with the closely spaced frontside device structures.
Solution Approach 2:
The patent divides the connection formation process into separate regions: frontside device areas and backside connection areas. The bulge region acts as a segmented transition zone that separates the frontside nanodevice structures from the backside via holes, allowing each region to be optimized independently for its specific function.
2Reliability
If source/drain contacts are formed with bulges towards the backside, then connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The bulge region is formed in advance during the source/drain contact formation process, before the backside via holes are created. This preliminary action prepares the connection interface in advance, ensuring proper alignment and contact between the frontside source/drain regions and the backside via holes, thereby improving connection reliability without requiring complex real-time adjustments.
3Reliability
If backside via holes are formed to connect to backside power rails, then short circuit risk is reduced, but patterning complexity increases
Solution Approach 1:
The patent extracts the connection formation process from the frontside device pattern area and relocates it to the backside substrate area. By taking out the via hole formation from the crowded frontside layout and performing it from the backside, the patterning can be done in a more open space, reducing the risk of tip-to-tip shorts between adjacent connections while managing the overall patterning complexity.
Data Source
AI summary
According to the embodiment of the present invention, a semiconductor device includes a first nanodevice including a plurality of first transistors and a second nanodevice including a plurality of second transistors. The first nanodevice includes a first source/drain contact having a first bulge towards a backside of the first source/drain contact. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. The first bulge is located between the first nanodevice and the second nanodevice. A backside via extends downwards from a backside of the first nanodevice and the second nanodevice to connect to a backside of the first bulge.