Backside Via Formation for Low-Resistance Semiconductor Contacts
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in maintaining the size and performance of backside vias, which affect contact resistance and device performance.
Innovation Solution
The formation of backside vias is initiated before substrate removal, followed by liner deposition and etching processes that maintain the width of the vias, enhancing silicide formation and contact area for improved contact resistance and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but backside via sizes are reduced leading to increased contact resistance and decreased device performance
Solution Approach 1:
The patent applies preliminary action by forming backside vias through the substrate before removing the substrate. This sequence allows the vias to be formed when the substrate is still present, providing structural support and enabling the use of standard via formation processes. The vias are formed with larger dimensions than would be possible if formed after substrate removal, thereby reducing contact resistance while still allowing high integration density on the front side of the device.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but via sizes are reduced leading to decreased silicide formation quality
Solution Approach 1:
The patent forms backside vias preliminarily before substrate removal, allowing silicide formation processes to be performed on via contacts that are still supported by the substrate structure. This preliminary formation enables better control of silicide deposition and annealing processes, achieving higher manufacturing precision for silicide contacts compared to forming vias at smaller dimensions after substrate removal.
3Productivity
If backside via sizes are reduced, then integration density can be increased, but contact area is decreased leading to increased contact resistance
Solution Approach 1:
The patent applies preliminary action by forming backside vias with larger cross-sectional areas before substrate removal. The substrate provides mechanical support that allows for larger via dimensions without compromising device structure. After substrate removal, these pre-formed larger vias maintain their larger contact areas, thereby reducing contact resistance while still enabling high integration density on the active device surface.
Solution Approach 2:
The patent utilizes the third dimension (depth) by forming vias that extend through the substrate thickness. By controlling via depth and cross-sectional area independently, the invention can maintain large contact areas at the substrate-backside interface while keeping the substrate thin enough to allow substrate removal and front-side high-density integration. This dimensional separation allows optimization of contact area without directly constraining front-side feature sizes.
Data Source
AI summary
A device includes a device layer including a first transistor, a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric material on the backside of the device layer, a contact extending through the first dielectric material to a first source/drain region of the first transistor, and a first conductive layer including a first conductive line electrically connected to the first source/drain region through the contact.