Backside Via Formation in Nanosheet Semiconductors With Spacer-Masked Etching
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, the reduction in feature size leads to challenges such as increased damage to interfaces between epitaxial source/drain regions and underlying layers during the etch process, resulting in reduced manufacturing yield and increased vulnerability to electrostatic discharge.
Innovation Solution
The formation of a dummy semiconductor layer on a nanosheet stack with sidewall spacers that mask end portions, allowing for preferential etching of the topmost layer while protecting the interfaces, thereby reducing damage and enhancing process variability during the formation of backside vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but damage to interfaces between epitaxial source/drain regions and underlying layers increases during etching
Solution Approach 1:
A dummy semiconductor layer is formed on the nanosheet stack before the etch process to protect the interface between epitaxial source/drain regions and underlying layers. This preliminary protective layer prevents direct exposure of the interface to etching, thereby reducing damage while enabling continued miniaturization for high integration density
Solution Approach 2:
The dummy semiconductor layer acts as an intermediary between the etch process and the sensitive interface regions. It serves as a sacrificial layer that absorbs etching damage, protecting the critical interface between epitaxial source/drain regions and channel layers while allowing the etch to proceed for via formation
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing yield decreases due to increased interface damage
Solution Approach 1:
The dummy semiconductor layer is formed in advance on the nanosheet stack to preemptively protect vulnerable interfaces during subsequent etching operations. This preliminary protection measures prevents yield loss by ensuring interface integrity is maintained even as feature sizes are reduced for higher integration density
Solution Approach 2:
The dummy semiconductor layer provides beforehand cushioning by absorbing etching damage that would otherwise directly affect the interface between epitaxial source/drain regions and underlying layers. This cushioning effect maintains manufacturing yield by preventing catastrophic interface damage during the etch process
3Ease of manufacture
If conventional etching is used without protective measures, then the process is simpler and faster, but damage to interfaces increases and process variability worsens
Solution Approach 1:
The dummy semiconductor layer is formed as a preliminary step before etching, adding minimal complexity to the overall process. This simple additional layer provides substantial protection to interfaces, significantly reducing damage without requiring complex process modifications or multiple etching steps
Solution Approach 2:
The dummy semiconductor layer functions as a disposable sacrificial layer that is intentionally designed to be removed after serving its protective function. This temporary layer absorbs etching damage at low cost, protecting the permanent interface structures while allowing the etch process to proceed with high precision
Data Source
AI summary
A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.