Backside Via Interconnects for Stacked FET Source/Drain Routing
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving compactness, efficient manufacturing, and minimizing thermal damage and contamination during the formation of stacked transistor devices.
Innovation Solution
A method for forming a semiconductor device involving a stack of field effect transistors (FETs) with a via and interconnect structure, where the via is formed by etching a hole laterally spaced from the FETs and filled with conductive material, and the interconnect is formed by etching a trench from the substrate side, connecting the source/drain region to the via, thereby reducing the vertical distance and avoiding unnecessary heating and contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional planar semiconductor devices are used, then manufacturing is simpler, but area efficiency and power efficiency are reduced
Solution Approach 1:
The patent transitions from traditional planar (2D) semiconductor device architecture to a vertical (3D) stacked transistor architecture. Multiple transistor layers are stacked vertically on top of each other, utilizing the third dimension to increase area efficiency while maintaining manufacturing compatibility through sequential layer formation processes.
2Reliability
If stacked transistor devices are formed with traditional routing, then connectivity is achieved, but thermal damage to metal contacts and dielectric layers increases
Solution Approach 1:
The patent inverts the traditional routing approach by forming vias and interconnects from the backside of the substrate rather than from the frontside. This backside access method allows interconnect formation without requiring lateral routing that would pass near sensitive metal contacts and dielectric layers, thereby reducing thermal damage during subsequent processing steps.
Solution Approach 2:
The patent performs via formation and interconnect routing as preliminary actions before forming the stacked transistor structures. By establishing the interconnect architecture first through backside access, the design avoids subsequent heating and contamination issues that would affect already-formed metal contacts and dielectric layers during later transistor fabrication steps.
3Ease of manufacture
If lateral interconnects are used for routing, then connectivity is achieved, but device area increases and manufacturing complexity increases
Solution Approach 1:
The patent eliminates lateral interconnect routing by transitioning to vertical interconnects through backside access. Vias are formed vertically through the substrate from the backside, and interconnect layers are stacked vertically, replacing extended lateral routing paths with compact vertical connections that reduce device area while simplifying the manufacturing process.
4Reliability
If frontside via formation is used, then connectivity is achieved, but contamination increases
Solution Approach 1:
The patent inverts the via formation approach by accessing the substrate from the backside rather than the frontside. This backside via formation method allows metal deposition and via filling without exposing the frontside metal contacts and dielectric layers to potential contamination sources, thereby reducing metal contamination while maintaining connectivity.
Data Source
Figure 1
Figure 2a~2d
Figure 3a~3d
AI summary
A method (100) for forming a semiconductor device (1), the method comprising: forming a stack of field effect transistors (60), FETs, on top of a substrate (4), the stack of FETs comprising a bottom FET (61) and a top FET (62), the bottom FET (61) comprising at least a first source/drain region (51); forming a first insulating layer (11) laterally surrounding the stack of FETs (60); etching a hole (20) into the first insulating layer (11), the hole (20) extending between a top endpoint (26) and a bottom endpoint (25); filling the hole (20) with electrically conductive material such that the electrically conductive material of the filled hole (20) forms a via (21); etching, from a bottom side (4b) of the substrate (4) towards the first insulating layer (11), a trench (30), such that a top part (30p) of the trench (30) comprises both a bottom side (51b) of the first source/drain region (51) and the bottom endpoint (25); filling the top part (30p) of the trench (30) with electrically conductive material, such that the electrically conductive material of the filled top part (30p) of the trench (30) electrically connects the bottom side (51b) of the first source/drain region (51) to the bottom endpoint (25) of the via (21).