Backside Wafer Thinning With Two-Step CMP Selectivity
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Solution Overview
Problem
Current semiconductor manufacturing methods rely on silicon-on-insulator (SOI) substrates or silicon substrates with etch stop layers, which are costly and limit production volume due to availability constraints.
Innovation Solution
A two-step chemical mechanical polish (CMP) process is used to selectively remove device wafer material overlying the active device area during backside processing, eliminating the need for SOI or silicon substrates with etch stop layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI substrates or silicon substrates with etch stop layers are used, then device characteristics are maintained, but manufacturing cost increases and production volume is limited
Solution Approach 1:
The patent changes the removal rate parameter as a function of depth in the CMP process. By tuning the CMP process to have depth-dependent removal rates, the method selectively removes device wafer material from the backside while preserving the active device area, eliminating the need for expensive SOI substrates or etch stop layers
Solution Approach 2:
The patent extracts and removes the device wafer material (bulk silicon) from the backside of the substrate using the tuned CMP process. This extraction of unnecessary material eliminates the need for special stop layers while maintaining device integrity
2Reliability
If SOI substrates or silicon substrates with etch stop layers are used, then device characteristics are maintained, but production volume is limited due to availability constraints
Solution Approach 1:
By changing the CMP process parameters to achieve depth-dependent selective removal, the patent enables processing of standard silicon substrates without special layers, thereby removing availability constraints and enabling higher production volumes
3Loss of time
If a single CMP process is used, then processing time is reduced, but selective removal of device wafer material over active device area is not achieved
Solution Approach 1:
The patent segments the CMP process into multiple steps with different parameters. The first CMP process uses a first set of parameters for initial material removal, while the second CMP process uses a second set of parameters optimized for selective removal over the active device area. This segmentation achieves both selective precision and reasonable processing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces manufacturing costs, eliminates availability constraints of SOI and silicon substrates with etch stop layers, and maintains or improves device characteristics.
Implementation Method 1
A first chemical mechanical polish (CMP) process is performed on the backside surface of the device wafer to thin the device wafer from the second thickness to a third thickness
Implementation Method 2
A second CMP process is performed on the backside surface of the device wafer to selectively remove device wafer material that is disposed over an active device area of the semiconductor device, where a removal rate of the device wafer material is a function of depth
Data Source
AI summary
A method of manufacturing a semiconductor device includes performing one or more grinding processes on a backside surface of a device wafer to thin the device wafer from a first thickness to a second thickness. A first chemical mechanical polish (CMP) process is performed on the backside surface of the device wafer to thin the device wafer from the second thickness to a third thickness. A second CMP process is performed on the backside surface of the device wafer to selectively remove device wafer material that is disposed over an active device area of the semiconductor device, where a removal rate of the device wafer material is a function of depth.