Backside Wiring Layout for Semiconductor Power Delivery

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Solution Overview

Problem

Existing semiconductor devices face challenges in design complexity and integration, necessitating improved ease of design and performance, particularly in high-reliability and high-speed applications.

Innovation Solution

The semiconductor device incorporates a backside wiring pattern with a backside wiring structure and through plugs that connect to frontside electronic devices, enhancing electrical connectivity and power delivery through a power delivery network, allowing for simplified design and improved performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If structures in the semiconductor device are increasingly complicated and highly integrated to meet high reliability, high speed, and multi-functionalization requirements, then performance is improved, but design complexity increases and easiness in design deteriorates

Engineering Contradiction:
Improvehigh reliabilityVSAvoiddesign complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the wiring structure into frontside wiring and backside wiring located on opposite surfaces of the substrate. This segmentation allows complex interconnections to be distributed across two surfaces, reducing the complexity of routing on a single surface while maintaining high integration and reliability requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar wiring structure to a three-dimensional structure by utilizing both frontside and backside surfaces of the substrate. This dimensional change enables more efficient routing and interconnection paths, improving reliability and performance while managing design complexity through spatial distribution.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If through plugs and vertical plugs with varying resistivities are incorporated to enable efficient power delivery and voltage regulation, then performance is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvepower delivery efficiencyVSAvoidmanufacturing complexity
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent applies local quality by incorporating vertical plugs with different resistivity values at specific locations within the interlayer insulating layer. These plugs with varying resistivities are strategically positioned to provide voltage regulation and efficient power delivery to different regions, allowing optimized electrical characteristics where needed while maintaining standard manufacturing processes.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent utilizes parameter changes by varying the resistivity of vertical plugs to achieve different electrical functions. By controlling the resistivity parameter of plugs at different locations, the design enables both low-resistance power delivery paths and high-resistance voltage regulation elements using the same basic plug structure and fabrication approach.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4362074B1Semiconductor device and method for fabricating the same
Publication Date: 2026.04.22 SAMSUNG ELECTRONICS CO LTD
  • EP4362074B1 patent drawingFigure 1
  • EP4362074B1 patent drawingFigure 2
  • EP4362074B1 patent drawingFigure 3

AI summary

A semiconductor device includes a substrate (100) including a frontside (100a) and a backside (1 00b) opposite the frontside, an electronic device (TR1; TR2) on the frontside of the substrate (100), an interlayer insulating layer (110) covering the electronic device (TR1; TR2), a frontside wiring structure (FS) on the interlayer insulating layer (110), a backside wiring structure (BS) on the backside of the substrate (100), and at least one unit chain (UC) connecting the electronic device (TR1; TR2) with the backside wiring structure (BS), the unit chain (UC) including a through plug (TP2) passing through the substrate (100), a connection contact (CC) on the interlayer insulating layer (110), a first chain plug (VP21) passing through the interlayer insulating layer (110) to connect the through plug (TP2) with the connection contact (CC), and a second chain plug (VP22) passing through the interlayer insulating layer (110) to be connected to the through plug (TP2).