Bake Plate Simulator Optimizing Critical Dimension Uniformity
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Solution Overview
Problem
The existing semiconductor manufacturing processes face challenges in achieving uniform post-exposure bake temperature and time across a wafer, leading to variations in photoresist hardening and critical dimensions, which affect the quality of integrated circuits due to wafer-to-wafer and within-wafer variations.
Innovation Solution
A system and method that utilizes a bake plate simulator, finite element analysis, and lithography emulator to optimize bake plate settings by simulating temperature distribution and critical dimension metrology, allowing for precise control of post-exposure bake processes to achieve uniformity across the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pre-calculated control parameters and indirect measurements are used for post exposure baking, then the baking process can be performed with simple control, but wafer-to-wafer variations and within-wafer variations cannot be accounted for, leading to non-uniform photoresist hardening
Solution Approach 1:
The bake plate is divided into multiple heating zones with independent temperature control. This segmentation allows different regions of the wafer to receive customized heating, compensating for wafer-to-wafer and within-wafer variations to achieve uniform photoresist hardening across the entire wafer surface.
Solution Approach 2:
Different zones of the bake plate are assigned different temperature settings based on local requirements. The system applies local quality control by adjusting temperature in specific regions to account for variations in wafer properties, ensuring each area receives the appropriate heating for uniform hardening.
2Manufacturing precision
If post exposure bake time is extended to ensure thorough hardening, then photoresist hardening quality improves, but processing time increases and productivity decreases
Solution Approach 1:
The bake plate temperature is dynamically adjusted during the post exposure bake process. The system transitions from static pre-calculated parameters to dynamic, real-time temperature control, allowing optimization of hardening quality while minimizing processing time through adaptive heating strategies.
Solution Approach 2:
The system incorporates feedback mechanisms that monitor the baking process and adjust temperature parameters accordingly. This feedback control enables the system to achieve thorough photoresist hardening in optimized time by responding to actual process conditions rather than relying on fixed pre-calculated parameters.
3Productivity
If higher temperature is used to reduce bake time, then processing efficiency improves, but temperature uniformity across the wafer becomes harder to maintain, affecting critical dimensions
Solution Approach 1:
The heating system is segmented into multiple independently controlled zones that can operate at different temperatures. This allows the system to use higher overall temperatures for faster processing while maintaining local temperature uniformity across different wafer regions, preventing critical dimension variations.
Solution Approach 2:
The system changes temperature parameters dynamically across different zones and time periods. By adjusting temperature parameters in a controlled manner across segmented zones, the system achieves both high processing speed and uniform critical dimensions through coordinated parameter management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more accurate and uniform photoresist hardening, improving the fidelity of image transfer and quality of integrated circuits by optimizing bake plate settings and temperature control, thereby reducing linewidth variations and enhancing chip yield.
Implementation Method 1
The simulation module includes a bake plate simulator that simulates temperature distribution across a wafer during post-exposure bake
Implementation Method 2
The finite element analysis calculates temperature and stress distribution in the wafer during heating
Data Source
AI summary
A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.