Detecting Faulty Computer Hardware TRIZ Cases

A recursive hierarchical static timing analysis method iterates lower and upper block constraints to reduce runtime.

Pruning signal flow graphs isolates sensitivity paths, reducing ultra-large circuit verification complexity from exponential to near-linear.

Hierarchical noise analysis generates abstract files with pin tolerances to detect external source failures without adding buffers.

A test module generation apparatus creates executable test programs from user-selected methods and condition files.

A shared bus diagnosis system applies an indicator to a vector of signal amplitude thresholds to detect faults.

Prioritizing mutated program execution via simplicity criteria reduces evaluation time while maintaining detection quality.

A method modeling current flows in three-dimensional conductive bodies using derived surface impedance values on planar bounding surfaces.

Test circuit selectively performs error correction and redundancy repair based on TMRS information, reducing chip size overhead.

Unified rack graphs map EID and SID to position faulty disks without unique machine-specific configurations.

Integrated detection units in the display controller detect circuit errors, reducing development cycles and area overhead.

A USB controller detects device capabilities and adjusts enumeration timing to ensure accurate protocol identification.

Start-of-packet and end-of-packet molecules distinguish mission data from non-mission data, reducing power consumption during gap cycles.

A method projects simulation traces over predicates to generate logical assertions for hardware design verification.

A chessboard graph organizes imaging parameters to evaluate resist model calibration accuracy across integrated circuit layouts.