Recursive Hierarchical Static Timing Analysis for IC Design
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Solution Overview
Problem
Hierarchical design flows in integrated circuit design face challenges in accurately establishing timing budgets for functional blocks and managing timing constraints between lower-level and top-level blocks, leading to a lack of confidence in static timing analysis results and lengthy STA runtimes.
Innovation Solution
A recursive hierarchical static timing analysis method that iteratively performs static timing analysis on lower-level and upper-level blocks, incorporating feedback to update constraints and using model abstraction levels, while performing design rule checking to ensure accuracy and consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If hierarchical design flows are used to divide circuit netlist into blocks, then device complexity is reduced and ease of manufacture is improved, but timing budget establishment becomes difficult and timing constraint management between blocks becomes complex
Solution Approach 1:
The patent divides the circuit netlist into hierarchical blocks (first-level blocks, second-level blocks, etc.) and performs static timing analysis on each block separately. This segmentation allows timing budgets to be established at the block level rather than for the entire circuit, making the timing constraint management more manageable while preserving the benefits of hierarchical design for reducing overall system complexity.
2Ease of operation
If hierarchical design with blocks is used, then ease of operation is improved for design allocation and reuse, but confidence in static timing analysis results deteriorates due to difficulty in managing timing constraints
Solution Approach 1:
The patent performs static timing analysis on lower-level blocks before analyzing upper-level blocks. By establishing timing characteristics of subordinate blocks first, the system prepares timing data and constraints in advance that can be reliably used in higher-level analysis, ensuring that timing budgets are properly propagated through the hierarchy and confidence in results is maintained.
Solution Approach 2:
The patent uses timing analysis results from lower-level blocks as feedback to refine and update timing constraints for upper-level blocks. This iterative feedback process ensures that timing budgets are consistently applied across all hierarchical levels, maintaining reliability of STA results while preserving the operational benefits of hierarchical design for allocation and reuse.
3Measurement precision
If conventional flat STA process is used, then accuracy and confidence in results are maintained, but STA runtime becomes excessively long and productivity is reduced
Solution Approach 1:
The patent segments the static timing analysis process into hierarchical blocks, analyzing smaller sub-circuits separately rather than analyzing the entire circuit at once. This segmentation dramatically reduces the computational complexity and runtime of STA while maintaining accuracy by ensuring that timing constraints are properly propagated between blocks through the hierarchical structure.
Data Source
AI summary
A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block. Subsequently, recursive static timing analysis is performed on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block.