Hardware Assertion Generation via Trace Projection
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Solution Overview
Problem
Existing methods for generating assertions in hardware design verification are either syntactically based and fail to capture real functional behaviors, or rely on inefficient brute-force approaches that are slow and produce many false warnings, making them time-consuming and error-prone.
Innovation Solution
A method that automatically generates assertions by projecting trace data over a set of predicates, computing states as a logical formula, and enumerating logical consequences as assertions, using techniques such as disjunctive normal form (DNF) and conjunctive normal form (CNF) to efficiently capture temporal behaviors of design elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If syntactical analysis is used to generate assertions based on pre-defined patterns, then assertion generation is automated, but the assertions fail to capture real functional behaviors and produce many false warnings
Solution Approach 1:
The patent introduces simulation traces as an intermediary between the hardware design and assertion generation. Instead of directly analyzing HDL syntax, the system first generates simulation traces by executing the design with test inputs, then derives assertions from these behavioral traces. This intermediary step captures the actual functional behavior of the design, resolving the contradiction between automation and accuracy.
Solution Approach 2:
The patent replaces the mechanical syntax-based analysis approach with a behavior-based approach using simulation traces. By substituting syntactical pattern matching with trace-driven analysis, the system achieves both automation and high accuracy in assertion generation, eliminating false warnings while maintaining automated assertion creation.
2Reliability
If brute-force approaches are used to enumerate and test candidate assertions, then comprehensive coverage is achieved, but the process is extremely time-consuming and inefficient
Solution Approach 1:
The patent extracts only the essential behavioral information from simulation traces that is relevant for assertion generation. Instead of exhaustively testing all possible candidate assertions, the system extracts key behavioral patterns and temporal relationships directly from the traces, then generates assertions based on these extracted patterns. This extraction approach achieves comprehensive coverage without the computational expense of brute-force enumeration.
Solution Approach 2:
The patent performs preliminary analysis of simulation traces to identify relevant behavioral patterns and temporal relationships before generating assertions. By pre-processing the trace data to extract meaningful patterns, the system avoids the need for time-consuming exhaustive testing of candidate assertions, thereby achieving both comprehensive coverage and high efficiency.
3Measurement precision
If manual assertion creation is used, then assertions can be precisely tailored to design requirements, but the process is time-consuming and error-prone
Solution Approach 1:
The patent implements self-service assertion generation by automatically deriving assertions from simulation traces of the hardware design. The system serves itself by extracting behavioral patterns and generating appropriate assertions without human intervention, achieving both high precision (by capturing actual design behavior) and high efficiency (by automating the entire process). This eliminates the time-consuming and error-prone manual assertion creation process.
Data Source
AI summary
One embodiment of the present invention provides a method that automatically generates assertions of a hardware design. The method includes accessing a trace and a set of predicates of the hardware design. Then, the trace is projected over the set of predicates to generate a second trace. Then, a new set of states of the second trace is computed and the result is represented as a logical formula. The formula is reduced by logic optimization techniques. And finally, a set of logical consequences of the logic formula is produced and each logical consequence is enumerated as an assertion.