Hierarchical Noise Analysis for Circuit Blocks
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Solution Overview
Problem
Conventional hierarchical noise analysis methods for integrated circuits fail to account for noise failures caused by external sources attached to output pins, leading to undetected malfunctions in circuit blocks due to noise feedback.
Innovation Solution
The proposed method generates noise abstracts for circuit blocks that include noise tolerances for input, bi-directional, and output pins, allowing for the analysis of noise-induced failures within the blocks and across units, using a three-step hierarchical noise analysis process that includes block, unit, and chip-level analyses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional hierarchical noise analysis is used, then analysis efficiency is improved, but noise failures caused by external sources attached to output pins are not detected
Solution Approach 1:
The patent segments the noise analysis into three distinct levels: block-level noise abstract generation, unit-level noise analysis, and chip-level noise analysis. This segmentation allows the analysis to handle complex circuits systematically while capturing noise failures at multiple hierarchies, including those caused by external sources attached to output pins.
Solution Approach 2:
The patent performs preliminary block-level noise analysis to generate noise abstracts that characterize noise behavior at the block level. These abstracts are then used in subsequent unit-level and chip-level analyses, allowing efficient propagation of noise failure information through the hierarchy while maintaining detection accuracy for external source failures.
2Reliability
If buffers are added to reduce noise, then noise immunity is improved, but circuit delay increases
Solution Approach 1:
The patent implements feedback mechanisms at each level of the hierarchical noise analysis to identify noise failures and their sources. By detecting noise failures caused by external sources attached to output pins and propagating this information through the hierarchy, the system can identify problematic areas without requiring additional buffers, thereby maintaining circuit speed while improving noise immunity through targeted design changes.
Data Source
AI summary
Systems and methods for the noise analysis of circuits are presented. These systems and methods may allow a circuit or circuit design to be analyzed for possible noise failures in a block of logic caused by sources. outside the block. More particularly, these systems and methods may generate an abstract file for one or more blocks of a circuit. These abstract files may include noise tolerances for input pins and bi-directional pins of a block, along with noise tolerances for those output pins of the block which also feed to an input of one or more gates internal to the block. Using these noise abstracts a unit of the circuit may be analyzed, or the circuit itself may be analyzed for possible noise induced failures.