Multi-dimensional Chessboard Graph for Resist Model Calibration
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Solution Overview
Problem
Accurately calibrating resist models for predicting the printing behavior of integrated circuit layouts is challenging due to the difficulty in ensuring that test mask patterns adequately represent the features of the desired circuit, leading to potential errors and failures in photolithographic processes.
Innovation Solution
A system that divides edge fragments of test and desired layout polygons into simulation sites, calculates imaging parameters, and displays them on a multi-dimensional chessboard graph for comparison, allowing users to determine if the resist model can be accurately calibrated and identifying any critical features that may not be accurately modeled.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a test mask pattern is used to calibrate the resist model, then the model can be calibrated, but it may not accurately represent all features in the desired integrated circuit layout
Solution Approach 1:
The patent transforms the comparison of test pattern and desired layout features from a traditional one-to-one matching approach into a multi-dimensional feature space analysis. By extracting multiple features (edge orientations, curvature, density, spacing) and organizing them into a multi-dimensional database, the system can comprehensively evaluate whether the test pattern adequately represents the desired layout across all relevant dimensions, rather than relying on simple visual or manual comparison.
Solution Approach 2:
The patent changes the parameters used for evaluating pattern representation from qualitative assessments to quantitative measurements. By calculating specific parameters such as edge fragment lengths, curvature values, feature densities, and spacing measurements at multiple simulation sites, the system objectively determines whether the test pattern captures the essential characteristics of the desired layout, thereby improving the reliability of model calibration.
2Reliability
If manual inspection of test patterns is used to ensure feature representation, then some features can be verified, but the process is time-consuming and incomplete
Solution Approach 1:
The patent replaces the manual mechanical inspection process with an automated computer-based system. The computer automatically extracts features from both the test pattern and desired layout, calculates imaging parameters at multiple simulation sites, and performs the comparison without human intervention. This substitution of manual inspection with automated computational analysis dramatically reduces the time required while improving the completeness and consistency of the verification process.
Solution Approach 2:
The system enables the test pattern to effectively evaluate itself against the desired layout through automated feature extraction and comparison. The computer system independently performs the entire verification process, from extracting geometric features to calculating imaging parameters and determining adequacy, without requiring continuous human oversight or manual measurement, thereby achieving rapid self-verification.
3Manufacturing precision
If comprehensive feature analysis is performed to ensure accurate model calibration, then prediction accuracy improves, but the complexity of the analysis process increases
Solution Approach 1:
The patent segments the complex analysis task into distinct, manageable components: (1) extracting geometric features from patterns, (2) dividing edges into fragments, (3) identifying simulation sites at specific locations, (4) calculating imaging parameters for each site, (5) organizing results in multi-dimensional databases, and (6) comparing features between test pattern and desired layout. This segmentation allows each component to be handled by specialized software modules, making the overall complex analysis process more systematic and manageable.
Data Source
AI summary
A system and method for determining whether a desired integrated circuit layout can be accurately modeled from a resist model that is calibrated from a mask test pattern. In one embodiment, a chessboard graph is created having horizontal and vertical axes that are assigned two imaging parameters calculated from the test mask data and the desired integrated circuit layout data. Data on the horizontal and vertical axes of the chessboard graph are divided into a number of ranges or bins. The intersection of each bin on the horizontal and vertical axis is associated with a subgraph that plots the relation between two additional imaging parameters having values of the first two imaging parameters in the ranges of the intersecting bin.


