Semiconductor Memory ECC Circuit for Defective Cell Repair
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Solution Overview
Problem
Conventional redundancy repair techniques for semiconductor memory devices require excessive redundancy, leading to increased chip size and inefficiency in addressing defective memory cells, and are not suitable for post-fabrication reliability and quality issues.
Innovation Solution
A semiconductor memory device with an on-chip or off-chip error correction code (ECC) system that generates parity bits during write operations and corrects errors during read operations, along with a test circuit for selective error correction and redundancy repair based on test mode register set information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional redundancy repair technique is used to replace defective memory cells, then defective cells can be repaired, but the chip size increases due to excessive redundancy requirements
Solution Approach 1:
The patent changes the approach from physical redundancy (adding extra memory cells) to logical redundancy (using ECC codes). By changing the parameter from physical cell count to error correction code capability, the system can repair defective cells without proportionally increasing chip area, as ECC operates on data bits rather than requiring separate physical backup cells for each defective cell.
Solution Approach 2:
Instead of creating physical copies of memory cells through redundancy circuits, the patent uses error correction codes that create logical copies through parity bits and syndrome information. The ECC system captures error patterns and reconstructs correct data without requiring physical duplicate cells, thereby reducing the area overhead compared to conventional redundancy repair.
2Reliability
If a redundancy repair technique is used, then defective cells can be addressed, but many cells are unnecessarily used to repair a 1-bit defect
Solution Approach 1:
The patent transitions from a parameter-based approach where multiple cells are allocated for redundancy to a code-based approach where ECC algorithms efficiently handle errors. The error correction code system can correct multiple bit errors using a minimal number of parity bits, thereby reducing the quantity of cells required compared to conventional redundancy techniques that would require allocating entire rows or columns for single-bit repair.
Solution Approach 2:
Instead of applying full redundancy coverage to all memory cells (excessive action), the ECC system applies error correction only where needed through selective parity checking and syndrome-based error identification. This partial action approach corrects errors in specific locations without requiring redundant structures across the entire memory array, thus reducing the total number of cells used.
3Ease of manufacture
If a redundancy repair technique is used, then repair capability is provided, but the technique is not suitable for coping with reliability problems caused after fabrication
Solution Approach 1:
The patent implements a dynamic error correction system using ECC that can adapt to various error patterns occurring after fabrication. Unlike static redundancy repair circuits that are fixed during manufacturing, the ECC system dynamically identifies and corrects errors through syndrome calculation and iterative decoding, enabling it to handle reliability problems that manifest after fabrication under different operating conditions.
Solution Approach 2:
The error correction code circuit serves multiple functions: it detects errors, locates defective cells, corrects single-bit and multi-bit errors, and can operate in different modes (correct-only, repair-only, or combined). This universal capability makes the ECC system more versatile for post-fabrication reliability problems compared to conventional redundancy repair techniques that are limited to specific error scenarios and require separate repair circuits for different error types.
Data Source
AI summary
A semiconductor memory device is provided which includes memory cells, a first error correction code (ECC) circuit configured to generate at least one selected parity bit corresponding to a selected data bit using an error correction code during a write operation and to correct an error of the selected data bit using the selected parity bit during a read operation, and a test circuit configured to selectively perform at least one of an error correction operation and a redundancy repair operation on at least one of the selected data bit and the selected parity bit based on test mode register set (TMRS) information.