Balanced 8T SRAM Cell for CFET Write Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SRAM designs face challenges in achieving performance and scalability goals, particularly in on-chip cache memories, due to difficulties in scaling memory capacity and bandwidth, and the vertical stacking of p-type and n-type MOSFETs in CFET technology results in inefficient write operations.
Innovation Solution
A balanced 8T SRAM cell design is implemented with four nMOSFETs and four pMOSFETs, optimizing the nMOS write port and pMOS read ports to achieve high density and symmetry, using CFET process technology to enable efficient read and write operations, and utilizing identical bit cell topologies across different Register File types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical stacking of p-type and n-type MOSFETs is used in CFET technology, then device density is improved, but write operation efficiency deteriorates
Solution Approach 1:
The patent applies asymmetry by creating an unbalanced transistor configuration where one port has stronger nMOS transistors and the other port has stronger pMOS transistors. Specifically, the first port uses nMOS transistors with higher drive strength for writing, while the second port uses pMOS transistors for reading, allowing each port to be optimized for its specific function rather than using symmetric balanced transistors
Solution Approach 2:
The patent implements local quality by assigning different transistor types and strengths to different ports based on their specific functional requirements. The write port uses nMOS transistors with higher drive strength locally optimized for writing operations, while the read port uses pMOS transistors locally optimized for reading operations, allowing each local region to have the properties needed for its function
2Ease of manufacture
If symmetric balanced SRAM cell design is used, then manufacturing simplicity is improved, but write performance deteriorates
Solution Approach 1:
The patent deliberately introduces asymmetry in the transistor configuration to resolve the contradiction between manufacturing simplicity and write performance. By having one port with nMOS transistors and the other with pMOS transistors, the design achieves easier manufacturing through standardized cell structures while simultaneously improving write performance through the asymmetric transistor strength configuration
3Strength
If nMOS write port is used, then write drive strength is improved, but read stability may deteriorate
Solution Approach 1:
The patent uses asymmetry to assign nMOS transistors specifically to the write port where high drive strength is needed, while assigning pMOS transistors to the read port where stability is prioritized. This asymmetric division allows each transistor type to operate in its optimal regime for its designated function
Solution Approach 2:
The patent applies local quality by optimizing the transistor configuration locally at each port: the write port receives nMOS transistors with high drive strength for efficient writing, while the read port receives pMOS transistors with characteristics optimized for stable reading operations
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
Embodiments herein relate to a balanced eight-transistor (8T) static random-access memory (SRAM) cell having four n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) and four p-type MOSFETS. An nMOS write port and two pMOS read ports are optimized with a complementary field-effect transistor (CFET) process to achieve a high density. The cell is reconfigurable for various port configurations including 1R1W (1-read 1-write), 2R1W (2-read 1-write), 3R1W (3-read 1-write), 4R1W (4-read 1-write) and single/dual-ported SRAM with appropriate Vt (voltage threshold) targeting.