Balanced Binary Encoding for Parallel Bus Noise Reduction
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Solution Overview
Problem
As computing platforms and integrated circuits experience increased transmission speeds and bus widths, power supply variations and noise become significant issues due to large changes in the ratio of '0' bits to '1' bits on parallel data buses, affecting signal integrity and error detection/correction.
Innovation Solution
Encoding data using codes with approximately equal numbers of '0' and '1' bits to stabilize power supply demands and reduce noise, implemented through a transmitting device with an encoder that generates six-bit codes from four data bits, ensuring balanced buffer activation and aiding in error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transmission speed and bus width are increased, then data transmission capacity is improved, but power supply variations and noise increase
Solution Approach 1:
The patent changes the parameter distribution of transmitted data by using encoding schemes that balance the number of '0' and '1' bits. This parameter change in the data representation reduces simultaneous switching activity, thereby reducing power supply variations and noise while maintaining high transmission capacity
Solution Approach 2:
The patent converts the harmful effect of high transmission speed (which causes noise) into a benefit by using the increased bandwidth to transmit encoded data with balanced bit patterns. The encoding transforms the problem of noise generation into an opportunity to improve signal integrity through controlled bit distribution
2Adaptability or versatility
If the ratio of '0' bits to '1' bits changes significantly in consecutive cycles, then data representation flexibility is improved, but power supply noise increases
Solution Approach 1:
The patent applies parameter changes by transforming the data representation to maintain a balanced ratio of '0' and '1' bits. Encoding schemes such as balanced ternary or differential encoding are used to ensure that consecutive data cycles have similar bit distributions, reducing power supply noise while preserving data representation flexibility
Solution Approach 2:
The patent introduces dynamic adaptation in the encoding process, where the encoder adjusts the bit pattern selection based on previous transmission cycles to maintain balanced ratios. This dynamic approach allows flexible data representation while actively controlling power supply noise through adaptive bit distribution
3Reliability
If error detection and correction capabilities are enhanced, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by incorporating error detection capabilities directly into the encoding process. Check bits and validation patterns are added during the encoding stage rather than requiring separate complex error correction circuits, thereby improving data reliability while minimizing additional device complexity
Solution Approach 2:
The patent achieves multi-functionality by designing encoding schemes that simultaneously perform data representation, power noise reduction, and error detection. The same balanced bit pattern encoding that reduces power supply variations also provides inherent error detection capabilities, eliminating the need for separate error correction hardware
Data Source
AI summary
Embodiments for binary encoding and/or decoding data are disclosed. In or more embodiments, N data bits may be encoded using one of a plurality of codes derived from at least N+1 bits wherein each of the plurality of codes comprises approximately equal numbers of bits at a first logical level and a second logical level.