Balanced Flip-Flop Topology With Negative Feedback Against Bit Flips
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Solution Overview
Problem
Data flip-flops in safety-related systems, such as automotive and avionics, are susceptible to unintended state changes due to terrestrial radiation, which can compromise system safety by causing bit flips, failing to meet stringent failure-in-time (FIT) requirements.
Innovation Solution
The design incorporates latches with balanced transistor turn-on resistances between nodes and voltage rails, and negative feedback circuits that are gated to prevent interference with data writing, enhancing resistance to terrestrial radiation and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flip-flop design is used, then device complexity is low, but reliability is poor due to susceptibility to radiation-induced bit flips
Solution Approach 1:
The patent applies asymmetry by configuring the first latch with inverters having different effective W/L ratios (first W/L for first inverter, second W/L for second inverter where first W/L ≠ second W/L). This asymmetric configuration creates balanced transistor turn-on resistances at the output nodes, improving radiation tolerance while maintaining manageable device complexity.
Solution Approach 2:
The patent implements local quality by applying different effective W/L ratios to specific inverters within the latch structure. The first and second inverters have one effective W/L ratio while the third and fourth inverters have another effective W/L ratio, creating localized electrical characteristics that balance the overall circuit performance and enhance reliability against radiation effects.
2Reliability
If balanced transistor turn-on resistances are implemented, then reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses parameter changes by systematically varying the effective W/L ratios of different inverters in the latch. By setting specific relationships between the effective W/L ratios (first W/L for first/second inverters, second W/L for third/fourth inverters), the design achieves balanced turn-on resistances without requiring all transistors to be identical, thus improving reliability while managing manufacturing precision requirements.
Data Source
AI summary
The disclosure relates to a latch including a first inverter with a first pair of field effect transistors (FETs) configured with a first channel width to length ratio (W/L), and a second inverter with a second pair of FETs configured with a second W/L different than the first W/L. Another latch includes first and second inverters; a first negative feedback circuit including first and second FETs coupled between first and second voltage rails, the input of the first inverter coupled between the first and second FETs, and the first and second FETs including gates coupled to an output of the first inverter; and a second negative feedback circuit including third and fourth FETs coupled between the first and second voltage rails, the input of the second inverter coupled between the third and fourth FETs, and the third and fourth FETs including gates coupled to an output of the second inverter.