Balanced Read Disturb Management in NAND Flash Memory

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Solution Overview

Problem

NAND Flash devices suffer from read disturbances due to physical defects, leading to logical errors caused by the accumulation of threshold voltage increases in memory cells, which results in read disturb errors, and existing management techniques are inefficient, impacting performance and power consumption.

Innovation Solution

A balanced multi-level read disturb management algorithm that efficiently scans memory cells and relocates data to prevent degradation by proactively rewriting data when a read stress threshold is reached, using a controller to manage operations in software, firmware, or physical circuitry, and employing a data structure with multiple thresholds to optimize read performance and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If read operations are performed frequently on NAND Flash memory cells, then data access speed is improved, but threshold voltage accumulation causes read disturb errors

Engineering Contradiction:
Improvedata access speedVSAvoidread disturb errors
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by proactively detecting read disturbance conditions through monitoring read counts and threshold voltage changes, and performing data relocation before actual read errors occur. The controller predicts when read disturb will happen and takes preventive measures by relocating data to fresh blocks, thus maintaining both high read speed and data reliability.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If existing read disturb management techniques are used, then read disturb errors are reduced, but performance and power consumption are negatively impacted

Engineering Contradiction:
Improveread disturb error reductionVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements self-service by enabling the memory system to autonomously manage its own read disturb protection through integrated monitoring and relocation operations. The controller automatically tracks read counts, identifies vulnerable data, and performs selective relocation without requiring external intervention or complex host software, thereby reducing performance overhead while maintaining reliability.

Inventive Principle:
Principle #25Self-service

3Reliability

If existing read disturb management techniques are used, then read disturb errors are reduced, but power consumption increases

Engineering Contradiction:
Improveread disturb error reductionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by performing read disturb management selectively only on memory blocks that exhibit actual read disturbance characteristics. Instead of uniformly managing all blocks, the controller identifies specific blocks with high read counts or threshold voltage drift and applies relocation operations only to those, thereby reducing overall power consumption while maintaining effective read disturb protection where needed.

Inventive Principle:
Principle #3Local quality

4Reliability

If proactive data relocation is performed, then memory cell degradation is prevented, but operation complexity increases

Engineering Contradiction:
Improvememory cell degradation preventionVSAvoidoperation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service by integrating the read disturb detection and relocation logic directly into the memory controller, allowing the system to autonomously manage its own health without external intervention. The controller automatically monitors read counts, detects threshold voltage changes, and performs selective data relocation, thereby preventing memory cell degradation while keeping the operational interface simple for the host system.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11763899B2Balanced three-level read disturb management in a memory device
Publication Date: 2023.09.19 MICRON TECHNOLOGY INC
  • US11763899B2 patent drawing
  • US11763899B2 patent drawing
  • US11763899B2 patent drawing

AI summary

Methods, systems, devices, and computer-readable media for performing read disturb management of a memory device. A method includes retrieving a value of a read counter for a block associated with a read request issued to a memory array; refreshing valid word lines in the block if the value of the read counter exceeds a first threshold; identifying a set of valid word lines in the block if the value of the read counter exceeds a second threshold, the second threshold lower than the first threshold; identifying a subset of the set of valid word lines, the subset of the set of valid word lines including word lines having an error rate above a pre-configured error rate threshold; and refreshing the subset of the set of valid word lines.