Read-Only Memories TRIZ Cases

Applying an offset pulse before the target pulse reduces word line loading time, resolving delays caused by voltage generation circuit distance.

Flash memory devices adjust program voltage based on skipped bit detection to resolve the contradiction between high storage capacity and reliable programming.

A memory controller selects erase regions based on valid page counts to reduce data movement overhead.

A semiconductor filter circuit with a switchable capacitor network rapidly stabilizes control voltage, reducing wait time during mode transitions.

A ROM memory device lowers bit line precharge voltage to reduce energy use during read operations.

A memory device adjusts programming time based on operational phases to balance data integrity and performance.

Dynamic write driver selection reduces power consumption by reprogramming only failed resistive memory cells after verification.

A high-voltage generator adjusts source line potential during programming operations to maintain stable electrical conditions across the memory cell array.

Applying unequal positive and negative gate voltages to IGZO ferroelectric memory cells increases threshold voltage differences and widens the memory window.

Storing training settings in non-volatile memory eliminates re-training delays when returning from reduced-power states, maintaining device productivity.

Dynamic error correction schemes adjust page sizes based on bad column counts, enabling storage in high-defect memory blocks.

A page buffer latches data by detecting the time at which a sensing node potential decreases from a first level to a second level.

Switched bias control stabilizes voltage lines during sense amplifier operation, reducing abrupt current consumption and noise interference.

Pre-charging bit lines with a stable current prevents voltage drops from leakage, avoiding unintended adjacent cell programming.

A nonvolatile memory control circuit applies differentiated read pass voltages to unselected word lines based on their position relative to the selected cell.

Concurrent write and verify operations in non-volatile memory arrays reduce timing overhead for synaptic weight tuning.

A flash memory device generates soft information locally to reduce data bits transferred to the controller.

A flash memory programming method reprograms selected cells to increase threshold voltages and widen read margins between states.

A nonvolatile memory device counts cells using a shifting measurement window to maintain interval width during sequential sensing operations.

Selective negative wordline voltages mitigate neighbor gate effects and reduce unnecessary current consumption in recessed channel transistors.

Dividing memory cell clusters into a hierarchical bit line structure reduces load capacitance, which improves operating speed and decreases power consumption.

Determines optimal solid state storage thresholds using bit flip counts at bin bounds to avoid implausible flips and improve convergence.

Selective copyback operations using an intermediary buffer reduce error rates during transfers between heterogeneous non-volatile memory cells.

A low-dropout regulator uses a digital comparator to drive a switching transistor for fast transient response.

Multi-level cell memory arrays adjust program-verify thresholds via chunk-based measurements to widen read margins and improve reliability.

Segmented latch storage increases critical charge and N+ area, minimizing soft error rates caused by neutron strikes in reduced transistor sizes.

A non-volatile memory programming method incrementally adjusts threshold voltage to reduce coupling effects between adjacent cells.

A charge pump circuit uses intermittent voltage monitoring to reduce power consumption in semiconductor storage devices.

Counting undererased cells during erase detection identifies defective word lines, reducing verification time and read errors in non-volatile memory operations.

A block switch circuit generates select signals to apply erase bias voltage simultaneously across multiple memory blocks.

Repurposing dummy memory cells for source line grounding reduces die space and complexity while improving reliability.

An initial read operation stores set information in a latch, while determination units verify data accuracy to prevent errors from default DC levels.

Interleaved mat access in NOR-NAND flash memory keeps wordlines active during read operations to sustain data transfer rates.

A control means trims program verify voltages based on threshold voltage distributions across data states in memory cells.

A flash memory program method uses secondary programming to secure read margins between adjacent states.

A reference voltage generation circuit with a guarantee portion monitors node voltages to ensure accurate output levels.

A programming method sets threshold voltages within specific distributions to store multi-bit data in non-volatile memory cells.

Controlling voltage rising times and levels for selected and non-selected cells reduces threshold voltage variation caused by hot carrier injection.

A control circuit applies program voltage to edge word lines to reprogram memory cells without erasing them.

Parallel programming of three-terminal memory cells via controlled gate-drain voltage reduces matrix value setting time, accelerating vector multiplication.

A control circuit accelerates programming of slow planes in multi-plane non-volatile memory by adjusting voltage pulse duration.

A memory device adjusts scanning resolution dynamically based on counter values to optimize resource usage.

A graph neural network predicts electrical characteristics of individual memory cells using location-based graph data.

A flash memory controller allocates data to blocks based on erase counts.

A controller adjusts threshold voltages of adjustment memory cells sharing bit lines with target cells to enhance error correction performance.

A semiconductor memory device shares electric charge between dies during standby to reduce operating current.

A multi-level read disturb management algorithm scans memory cells and relocates data to prevent degradation.

A digital signal timing detection mechanism evaluates memory states to lower energy consumption in integrated circuits.

A charge pump circuit monitors write voltage under load current to ensure accurate boosting before memory cell data writing.

Pre-programming selected multi-level cells narrows threshold voltage distribution, reducing erase failure rates and shortening program times.