ROM Memory Bit Line Voltage Segmentation for Power Reduction

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Solution Overview

Problem

Existing ROM memory devices face inefficiencies in power consumption during read operations due to the use of precharged bit lines at VDD voltage, which limits power savings and compatibility with higher voltage circuitry.

Innovation Solution

A ROM memory device design that selectively pulls bit lines towards a reference voltage (Vref) less than VDD, using programmable elements and sense amplifiers to reduce voltage swing and power consumption, while allowing sense amplifier outputs to remain at VDD for compatibility with higher voltage circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If bit lines are precharged to VDD voltage for read operations, then compatibility with higher voltage circuitry is maintained, but power consumption increases

Engineering Contradiction:

Improvecompatibility with higher voltage circuitryVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent divides the voltage domain into two segments: bit lines operate at Vref (lower voltage) while sense amplifier outputs operate at VDD (higher voltage). This segmentation allows each component to operate at its optimal voltage level, reducing overall power consumption while maintaining compatibility with higher voltage circuitry through the sense amplifier interface.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the operating voltage parameter of bit lines from VDD to Vref (a lower voltage level). This parameter change directly reduces power consumption during read operations since power is proportional to voltage squared, while the sense amplifier maintains output compatibility with VDD-level circuitry.

Inventive Principle:

Principle #35Parameter changes

2Stability of the object's composition

If bit lines are precharged to VDD voltage, then voltage swing range is maximized, but power consumption during read operations increases

Engineering Contradiction:

Improvevoltage swing rangeVSAvoidpower consumption during read operations

Core Design Contradiction:

Stability of the object's compositionVSUse of energy by moving object

Solution Approach 1:

The patent changes the bit line precharge voltage parameter from VDD to Vref. While this reduces the absolute voltage swing range on the bit line, it significantly reduces power consumption since power consumption is proportional to the square of voltage. The sense amplifier compensates for the reduced swing by providing full VDD-level output signals.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8611128B2ROM memory device

Publication Date: 2013.12.17 NXP USA INC

AI summary

A memory device includes a plurality of read only memory cells, a precharge circuit, and a sense amplifier. A read only memory (ROM) cell of the plurality of ROM cells is coupled to a word line and a bit line. The ROM cell comprises a transistor having a first current electrode coupled to receive a reference voltage, a second current electrode selectively coupled to the bit line based on the programmed state of the ROM cell, and a control electrode coupled to the word line. The precharge circuit is coupled to the bit line. The precharge circuit precharges the bit line to a precharge voltage, wherein the precharge voltage is less than the reference voltage. The sense amplifier is coupled to the bit line and to a power supply voltage terminal for receiving a power supply voltage, wherein the reference voltage is less than the power supply voltage.