Low-Dropout Regulator With Digital-Assisted Transient Control

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Solution Overview

Problem

Conventional low-dropout regulators (LDOs) face issues with low bandwidth, slow load transient response, high quiescent power, large decoupling capacitance, and high noise, particularly in three-dimensional (3D) NAND flash memory applications.

Innovation Solution

A low-dropout regulator design incorporating a first switching transistor, a comparator, and a Miller capacitor, along with a driving module that includes MOSFETs and current sources, to achieve high bandwidth, low quiescent current, and reduced noise, utilizing a digital-assisted analog approach to stabilize output voltage and improve transient response.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional analog LDOs are used to ensure output stability under different load conditions, then high quiescent power and large decoupling capacitance are required, but bandwidth is low and load transient response speed is slow

Engineering Contradiction:
Improveoutput stabilityVSAvoidload transient response speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The LDO is divided into analog and digital portions. The analog portion includes the switching transistor and output stage for voltage regulation, while the digital portion includes the comparator and control logic for fast transient response. This segmentation allows each portion to be optimized for its specific function, achieving both stability and fast response.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The LDO dynamically switches between analog and digital control modes based on load conditions. During normal operation, analog control maintains low noise and stability. During transient conditions, digital control provides fast response through the comparator-driven switching transistor control.

Inventive Principle:
Principle #15Dynamics

2Reliability

If conventional analog LDOs are used to ensure output stability, then high quiescent power is required, but power consumption increases

Engineering Contradiction:
Improveoutput stabilityVSAvoidquiescent power
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The digital control portion operates periodically only when needed for transient response, rather than continuously. The comparator monitors output voltage and triggers switching transistor adjustments only during transient conditions, reducing overall power consumption while maintaining stability during normal operation.

Inventive Principle:
Principle #19Periodic action

3Speed

If digital LDOs are used to improve response speed, then bandwidth increases, but noise and switching power increase and architecture becomes complex

Engineering Contradiction:
Improveload transient response speedVSAvoidnoise
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The LDO separates digital and analog functions into distinct portions. The digital comparator handles transient detection and control logic, while the analog switching transistor and output stage handle voltage regulation. This segmentation confines digital noise to the control portion and prevents it from propagating to the clean analog output.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The switching transistor acts as an intermediary between the digital control signal and the analog output. It translates digital control commands into analog voltage adjustments, isolating the digital control logic from the analog output and preventing digital noise from contaminating the regulated output.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10423176B2Low-dropout regulators
Publication Date: 2019.09.24 YANGTZE MEMORY TECH CO LTD
  • US10423176B2 patent drawing
  • US10423176B2 patent drawing
  • US10423176B2 patent drawing

AI summary

A low-dropout regulator comprises a first switching transistor, a comparator, and a Miller capacitor. The first terminal of the first switching transistor is connected to a load, and the second terminal of the first switching transistor is connected to a power supply voltage. The first input terminal of the comparator is connected to a reference voltage, the second input terminal of the comparator is connected to the first terminal of the first switching transistor, and the output terminal of the comparator is connected to the control terminal of the first switching transistor. The first terminal of the Miller capacitor is connected to the control terminal of the first switching transistor, and the second terminal of the Miller capacitor is connected to the first terminal of the first switching transistor and the load.