Semiconductor Memory Wordline Driving Method for Leakage Control
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Solution Overview
Problem
The negative word line scheme in semiconductor memory devices increases current consumption and is affected by neighbor gate effects, particularly in transistors with recessed channel structures, leading to degradation in leakage current and off characteristics.
Innovation Solution
A method for driving semiconductor memory devices involves selectively applying different voltage levels to neighboring wordlines during active and precharge periods, using a main wordline decoder, sub wordline selection line decoder, and sub wordline drivers to manage voltage levels and reduce unnecessary current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a negative word line scheme is used to improve refresh characteristic, then leakage current is controlled without increasing threshold voltage, but current consumption increases due to increased potential variation width
Solution Approach 1:
The patent applies different voltage levels to different word lines based on their selection state. Selected word lines receive a first voltage level (VPP) while unselected word lines receive a second voltage level (VBBW, negative voltage). This local differentiation allows the negative word line scheme to be applied selectively rather than uniformly, improving refresh characteristic in selected cells while limiting current consumption by maintaining unselected word lines at negative potential without excessive voltage swing.
2Reliability
If the threshold voltage of a cell transistor is increased to reduce leakage current, then leakage current is reduced, but time taken to store data in the storage node is increased
Solution Approach 1:
The patent changes the voltage parameter of the word line from conventional ground level (0V) to negative voltage level (VBBW) during precharge state. This parameter change allows the cell transistor to maintain lower threshold voltage while still achieving leakage current reduction through the negative gate-source voltage relationship, thereby avoiding the time penalty associated with increased threshold voltage.
3Reliability
If negative word line scheme is applied to entire cell array, then neighbor gate effect is improved, but current consumption increases and off characteristics degrade in transistors with recessed channel structures
Solution Approach 1:
The patent implements selective application of negative word line voltage to specific regions or blocks of the cell array rather than uniformly to the entire array. This allows neighbor gate effect to be mitigated in areas where it is most problematic while limiting current consumption by restricting the negative voltage application scope. The selective approach also prevents excessive voltage stress on transistors with recessed channel structures.
Data Source
AI summary
A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.