Hierarchical Bit Line Structure for Semiconductor Memory
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high density, low power consumption, and fast operating speed due to increased bit line loading and load capacitance, which degrade performance and increase power consumption.
Innovation Solution
A semiconductor memory device with a hierarchical bit line structure is introduced, featuring reduced column pass gates, divided memory cell clusters, and a data path that transmits small swing data, reducing load capacitance and power consumption while increasing operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells connected to each bit line is increased to achieve higher density, then the capacity of the memory device is improved, but the load capacitance and loading resistance of the bit line increase, causing slower charge transfer and degraded performance
Solution Approach 1:
The patent divides the memory cell array into multiple blocks, where each block is independently connected to a bit line. This segmentation allows the memory device to achieve high overall density while maintaining low load capacitance per bit line, as each bit line only serves a limited number of memory cells within its block.
2Reliability
If conventional full-swing data techniques are used for data transmission, then data communication between memory cells and peripheral circuits is achieved, but the operating speed decreases and power consumption increases
Solution Approach 1:
The patent changes the voltage swing parameter from full-swing (0 to VDD) to small-swing (around VDD/2 with limited amplitude). This parameter change reduces the energy consumed during data transmission while maintaining sufficient signal integrity for reliable data communication between memory cells and peripheral circuits.
3Reliability
If full-swing data techniques are used for data transmission, then complete voltage levels are achieved for robust signaling, but the overall operating speed of the memory device decreases
Solution Approach 1:
The patent changes the voltage swing parameter from full-swing (0 to VDD) to small-swing (around VDD/2 with limited amplitude). This parameter change reduces the energy consumed during data transmission while maintaining sufficient signal integrity for reliable data communication between memory cells and peripheral circuits.
Data Source
AI summary
A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.