Non-volatile Memory Slow Plane Programming Acceleration
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Solution Overview
Problem
In multi-plane non-volatile memory systems, the programming speed is limited by the slowest plane, leading to inefficiencies in data storage as all planes must complete programming at the same rate, despite variations in manufacturing processes causing some planes to program faster than others.
Innovation Solution
Implementing a control circuit that identifies slow planes and applies an enhanced programming operation for the last data states, accelerating the programming process by adjusting the programming voltage pulse duration or magnitude specifically for these planes, allowing faster completion without affecting faster planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrent programming is applied to multiple planes, then productivity is improved, but the overall programming speed is limited by the slowest plane
Solution Approach 1:
The patent applies dynamic programming by adjusting the programming voltage pulse duration based on the actual programming speed of each plane. Fast planes use shorter pulses while slow planes receive extended pulses, allowing the system to adapt to variations in programming speed across different planes and eliminate the bottleneck effect of the slowest plane.
Solution Approach 2:
The patent changes the programming parameter (pulse duration) according to the performance characteristics of each plane. By monitoring the programming status and adjusting the pulse width dynamically, the system optimizes the programming speed for each plane individually, thereby improving overall productivity without being constrained by the slowest plane.
2Device complexity
If uniform programming pulse duration is applied to all planes, then device complexity is reduced, but programming time increases due to slow planes
Solution Approach 1:
The patent introduces variable programming pulse durations for different planes based on their programming speed characteristics. The control circuit monitors the programming status of each plane and adjusts the pulse width accordingly, extending pulses for slow planes and maintaining standard pulses for fast planes, thereby reducing overall programming time with minimal increase in control complexity.
Solution Approach 2:
The patent implements a feedback mechanism where the control circuit monitors the programming progress of each plane and uses this information to adjust the programming pulse duration. This feedback loop allows the system to identify slow planes and apply enhanced programming only where needed, optimizing programming time without requiring complex control for all planes.
3Speed
If enhanced programming is applied to all planes, then programming speed is improved, but energy consumption increases
Solution Approach 1:
The patent applies enhanced programming (extended voltage pulses) only to specific slow planes that require it, rather than uniformly to all planes. This localized approach ensures that additional energy is consumed only where necessary to accelerate programming, while fast planes continue to use standard pulse durations, thereby minimizing overall energy consumption while still improving programming speed where needed.
Data Source
AI summary
To increase the speed of programming of a multi-plane non-volatile memory, it is proposed to accelerate the programming of the last one or more data states for one or more slow planes.