Selective Sub-Block Erasure in Flash Memory

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Solution Overview

Problem

Existing memory device erase operations are inefficient as they require copying data from all valid pages of a memory block, and applying erase voltage can damage adjacent sub-blocks during sub-block erasure.

Innovation Solution

A method and device for selective sub-block erasure, where a first erase region is chosen based on the number of valid and invalid pages, using a recycle benefit index to minimize data copy overhead and avoid damaging adjacent sub-blocks by designating software-isolated sub-blocks to move valid data to other memory blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a whole memory block is erased, then all sub-blocks are cleared, but data in valid pages must be copied to other blocks first, reducing efficiency

Engineering Contradiction:
Improvedata integrityVSAvoiderase operation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory block is divided into multiple sub-blocks, allowing selective erasure of individual sub-blocks rather than erasing the entire block. This segmentation enables the system to erase only the necessary portions while preserving valid data in other sub-blocks, eliminating the need to copy data from all valid pages.

Inventive Principle:
Principle #1Segmentation

2Productivity

If erase voltage is applied to a sub-block, then that sub-block is erased, but adjacent sub-blocks may be damaged

Engineering Contradiction:
Improveerase operation efficiencyVSAvoiddata integrity in adjacent sub-blocks
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A drain select line is introduced as an intermediary component between sub-blocks. By controlling the drain select line state during erase operations, the system can electrically isolate adjacent sub-blocks, preventing erase voltage from affecting sub-blocks that are not intended to be erased while still enabling efficient sub-block level erasure.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If sub-block erasure is performed without isolation, then erase efficiency improves, but adjacent sub-block data is damaged

Engineering Contradiction:
Improveerase operation speedVSAvoiderase voltage interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

Before performing the erase operation on a target sub-block, the system preliminarily sets the drain select line to a specific state that electrically isolates adjacent sub-blocks. This preliminary action prevents harmful erase voltage interference from affecting neighboring sub-blocks before the actual erasure begins, enabling safe and efficient sub-block level operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9754637B2Erasing method and memory device using the same
Publication Date: 2017.09.05 MACRONIX INTERNATIONAL CO LTD
  • US9754637B2 patent drawing
  • US9754637B2 patent drawing
  • US9754637B2 patent drawing

AI summary

An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.