Dynamic Programming Time for NAND Memory Data Integrity
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Solution Overview
Problem
Non-volatile memory devices, such as NAND memory devices, face data retention degradation issues due to extended periods of storage, leading to reliability and functionality problems, especially in quad-level cell (QLC) devices with smaller threshold voltage margins, resulting in increased bit errors and potential data loss.
Innovation Solution
Implementing a dynamic programming time for memory devices, which allows switching between different programming times based on operational phases and trigger events, such as manufacturing, initialization, and end-user phases, to improve data integrity and mitigate data retention degradation without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If longer programming time is used during manufacturing and initialization phases, then data integrity is improved, but programming speed is reduced
Solution Approach 1:
The patent implements dynamic programming time adjustment by detecting operational phase trigger events (manufacturing, initialization, or end-user phase) and switching between different programming time values. The controller dynamically selects a first programming time for manufacturing/initialization phases to maximize data integrity, and a second programming time for end-user phases to maximize performance, thereby resolving the contradiction between reliability and productivity
Solution Approach 2:
The patent changes the programming time parameter based on detected trigger events indicating different operational phases. By adjusting this critical parameter dynamically rather than using a fixed value, the system optimizes data integrity when needed (manufacturing/initialization) and performance when needed (end-user operation), resolving the trade-off between reliability and productivity
2Productivity
If shorter programming time is used during end-user phases, then programming speed is improved, but data integrity is degraded
Solution Approach 1:
The system dynamically adjusts programming time based on the detected operational phase. During end-user phases, the controller selects a shorter second programming time to maximize programming speed and performance. This dynamic adaptation allows the system to prioritize productivity when data integrity risks are lower, while maintaining the ability to switch to longer programming times when integrity is critical
Solution Approach 2:
The patent modifies the programming time parameter dynamically based on trigger events that indicate the current operational phase. By changing this parameter from a fixed value to a dynamically adjusted value, the system achieves high programming speed during end-user operation while maintaining the capability to switch to more conservative timing when data integrity is paramount
3Reliability
If dynamic programming time switching is implemented, then both data integrity and performance are optimized, but device complexity is increased
Solution Approach 1:
The controller automatically detects trigger events indicating different operational phases and autonomously selects the appropriate programming time without external intervention. This self-service approach allows the system to optimize both data integrity and performance while keeping the control logic relatively simple, as the controller monitors its own operational state and makes adjustments based on predefined criteria
Solution Approach 2:
The system uses feedback from detected trigger events to adjust programming time dynamically. The controller monitors operational phase indicators and uses this feedback to select appropriate programming time values, creating a closed-loop control system that optimizes both reliability and productivity without requiring complex external control mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data integrity by using longer programming times during manufacturing and initialization phases to reduce errors and switches to shorter programming times during end-user phases to improve performance, effectively balancing data integrity and performance without degrading the memory device's functionality.
Implementation Method 1
applying a high positive voltage, which may be referred to as a 'program voltage,' a 'programming power voltage,' or 'VPP,' to a control gate to generate Fowler-Nordheim tunneling (referred to as 'F-N tunneling') between a floating gate and the semiconductor substrate
Implementation Method 2
applying a high negative voltage, which may be referred to as an 'erase voltage' or 'Vera,' to the control gate and a configured voltage to the bulk area to generate the F-N tunneling
Data Source
AI summary
In some implementations, a memory device may receive a write command indicating data to be programmed. The memory device may determine a programming time, from a first programming time and a second programming time, to be used to program the data, wherein the programming time indicates an amount of time to be associated with programming the data, and wherein the first programming time is associated with a first amount of time and the second programming time is associated with a second amount of time. The memory device may program the data to a memory of the memory device using the programming time.