NOR-NAND Flash Memory Interleaved Mat Access for Data Transfer

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Solution Overview

Problem

Flash memory devices, particularly NOR-NAND flash memory systems, face limitations in data transfer rates due to the restrictive nature of precharging operations in buffer memories, which hinder the enhancement of system performance.

Innovation Solution

The implementation of a buffer memory with a leveled wordline driving scheme, where selected wordlines are kept active until the completion of read operations for multiple memory cells, and precharging is done after deactivation, allowing for alternation between two mats to ensure sufficient precharging time without restricting data transfer rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If precharging is performed before each wordline activation in a buffer memory, then reliable data reading is ensured, but data transfer rate is restricted due to the time-consuming precharge operation

Engineering Contradiction:
Improvedata reading reliabilityVSAvoiddata transfer rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The buffer memory is divided into two separate mats (first mat and second mat). Each mat can independently perform read operations, allowing the system to alternate between mats and overlap precharging operations with active data transfer, thereby resolving the contradiction between reliable reading and high transfer rate

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system alternates between first and second mats in periodic fashion. While one mat is undergoing precharging, the other mat performs data transfer operations. This periodic switching allows precharging time requirements to be met without restricting overall data transfer rate

Inventive Principle:
Principle #19Periodic action

2Productivity

If data burst frequency is increased to achieve higher data transfer rate, then productivity improves, but precharge time cannot be completed within the reduced period

Engineering Contradiction:
Improvedata transfer rateVSAvoidprecharge time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

By segmenting the buffer memory into two independent mats, the system can perform precharging and data transfer operations in parallel across different mats, eliminating the time loss associated with sequential precharging operations

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs precharging operations in advance for one mat while simultaneously completing data transfer from another mat. This preliminary action ensures that precharging time requirements are met without compromising the data transfer rate

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7532521B2NOR-NAND flash memory device with interleaved mat access
Publication Date: 2009.05.12 SAMSUNG ELECTRONICS CO LTD
  • US7532521B2 patent drawing
  • US7532521B2 patent drawing
  • US7532521B2 patent drawing

AI summary

In a NOR-NAND flash memory device, data bits may be alternately selected from first and second mats. A selected wordline in a mat may be kept active until completing a read operation for data bits of more than one memory cells coupled to the selected wordline.