Asymmetric Programming of IGZO FeRAM Memory Cells
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Solution Overview
Problem
Existing methods for programming ferroelectric random-access memory (FeRAM) cells with metal oxide channels using gate voltages of opposite polarities and equal magnitudes result in limited threshold voltages and memory windows, requiring significant gate electrode work function adjustments.
Innovation Solution
An asymmetric programming method is employed, utilizing a first write operation with a gate voltage of positive polarity and a first magnitude, and a second write operation with a gate voltage of negative polarity and greater magnitude, allowing for higher threshold voltages and increased memory windows while reducing gate electrode work function adjustments to less than 0.5 electron-volts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If gate voltages of opposite polarities and equal magnitudes are used to program FeRAM cells, then the programming process is simple and symmetric, but the threshold voltage differences and memory windows are limited
Solution Approach 1:
The patent applies asymmetry by using gate voltages with opposite polarities but unequal magnitudes during programming operations. Specifically, one voltage has a first magnitude while the other has a second magnitude that is greater than the first, creating asymmetric programming conditions that achieve larger threshold voltage differences and wider memory windows compared to symmetric equal-magnitude approaches
2Manufacturing precision
If gate electrode work function adjustments are made to achieve higher threshold voltages, then memory window size increases, but the complexity and cost of device fabrication increase
Solution Approach 1:
The patent changes the voltage parameters during programming operations to achieve the desired threshold voltage differences without requiring complex work function adjustments. By using asymmetric voltage magnitudes (first magnitude and second magnitude where second > first) with opposite polarities, the method achieves larger memory windows through operational parameter changes rather than through complex device structure modifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more reliable determination of programmed logic levels in FeRAM cells by achieving greater threshold voltage differences, enhancing memory window size and reducing the need for large work function adjustments, compared to traditional methods.
Implementation Method 1
the dielectric layer includes a ferroelectric material and the device is referred to as a ferroelectric random-access memory (FRAM or FeRAM) cell
Implementation Method 2
a conductive channel of an NVM cell includes a high electron mobility material, e.g., a metal oxide such as indium gallium zinc oxide (IGZO)
Data Source
AI summary
A memory circuit includes a plurality of memory cells, each memory cell of the plurality of memory cells including a gate electrode, a ferroelectric layer adjacent to the gate electrode, a channel layer adjacent to the ferroelectric layer, the channel layer including indium gallium zinc oxide (IGZO), and source and drain contacts adjacent to the channel layer opposite the ferroelectric layer. The memory circuit is configured to, during write operations to a memory cell of the plurality of memory cells, apply a plurality of voltage levels to the gate electrode relative to a ground voltage level applied to the source and drain contacts, a first voltage level of the plurality of voltage levels has a positive polarity and a first magnitude, and a second voltage level of the plurality of voltage levels has a negative polarity and a second magnitude greater than the first magnitude.