Parallel Programming of Three-Terminal Memory Cells for Matrix Multiplication
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Solution Overview
Problem
The process of individually programming matrix values in three-terminal memory cells is time-consuming, which hinders the efficiency of vector matrix multiplication.
Innovation Solution
Simultaneously programming multiple three-terminal memory cells by controlling the gate-drain voltage to increase, decrease, or maintain the effective resistance of cells in parallel, allowing for faster programming of matrix values through controlled voltage sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If individual programming of each memory cell is performed, then programming precision is maintained, but programming time increases significantly
Solution Approach 1:
The patent merges multiple individual programming operations into a single parallel programming operation by applying a composite voltage waveform to multiple memory cells simultaneously. This combines the precision of individual cell programming with the speed of parallel operations, resolving the contradiction between programming precision and programming time.
Solution Approach 2:
The patent uses periodic voltage waveforms with specific timing characteristics to program multiple memory cells in parallel. The periodic nature of the voltage application allows simultaneous control of multiple cells while maintaining individual cell programming precision, thereby reducing overall programming time without sacrificing accuracy.
2Productivity
If parallel programming of multiple memory cells is implemented, then programming speed increases, but control complexity increases
Solution Approach 1:
The patent employs a universal voltage waveform generation mechanism that can simultaneously control multiple memory cells with different programming requirements. This multi-functional approach allows a single control system to handle parallel programming of multiple cells, increasing programming speed while managing control complexity through waveform design rather than complex control logic.
3Loss of time
If higher voltage pulses are applied to program cells faster, then programming time decreases, but risk of cell damage increases
Solution Approach 1:
The patent changes the voltage waveform parameters (amplitude, duration, shape) to achieve fast programming without exceeding cell reliability limits. By optimizing these parameters, the system reduces programming time while maintaining cell reliability, as the waveform is designed to stay within safe operating boundaries while still achieving the desired programming speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the time required to program the entire array, thereby speeding up the vector matrix multiplication process, particularly beneficial in neural network training applications.
Implementation Method 1
the physical state is determined by how much charge is floating in its gate. Therefore, each cell may be individually programmed by supplying voltage pulses to it until the stored charge, and the resulting current, corresponds to the value the cell is supposed to represent.
Implementation Method 2
Changing the amount of charge in the three-terminal memory cell changes the threshold voltage for allowing current flow between the source drain; hence for a given gate voltage, the amount of current that will flow from source to drain is altered when the amount of charge is altered.
Implementation Method 3
the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source, while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that each cell at the intersection of a row and a column experiences one of the following three conditions: Increase effective resistance, which is achieved for floating gate cells by adding charge thereto; Decrease effective resistance, which is achieved for floating gate cells by removing charge therefrom
Data Source
AI summary
A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.