Nonvolatile Memory Cell-to-Cell Interference Mitigation via Localized Read Pass Voltages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In nonvolatile semiconductor memory devices like NAND flash memories, the challenge is to reduce cell-to-cell interference due to scaling limitations, which affects the reliability of data read and write operations as the size of memory cells decreases, leading to increased electric field strength and potential differences between adjacent cells.
Innovation Solution
The implementation of a specific voltage application method during read operations, where read pass voltages are adjusted for unselected word lines relative to the selected word line, including applying higher read pass voltages to certain unselected word lines to compensate for floating gate potential variations, thereby reducing the potential difference between adjacent cells and alleviating breakdown voltage issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar scaling is advanced to decrease memory device size, then device density increases, but cell-to-cell interference increases due to higher electric field strength between adjacent cells
Solution Approach 1:
The patent applies different read pass voltages to different unselected word lines based on their position relative to the selected word line. Specifically, a first read pass voltage is applied to a first unselected word line while a second read pass voltage (different from the first) is applied to a second unselected word line. This local differentiation of voltage levels compensates for the varying degrees of cell-to-cell interference experienced by different unselected word lines, thereby maintaining reliable read operations despite planar scaling-induced interference.
2Area of stationary object
If word line pitch is scaled down to increase density, then area utilization improves, but electric field strength between word lines increases causing potential difference issues
Solution Approach 1:
The patent changes the voltage parameter applied to unselected word lines based on their position. By applying a first read pass voltage to a first unselected word line and a second read pass voltage to a second unselected word line, the patent dynamically adjusts electrical parameters to compensate for the increased electric field strength resulting from reduced word line pitch. This allows the device to maintain proper operation despite the higher electric fields caused by denser packing.
3Quantity of substance
If floating gate size is reduced to increase cell density, then storage capacity increases, but floating gate potential becomes more susceptible to adjacent cell control gate voltage
Solution Approach 1:
The patent applies preliminary compensatory voltages to unselected word lines during read operations. By applying different read pass voltages to different unselected word lines before the actual read operation, the patent pre-compensates for the potential interference that would otherwise affect the floating gate potential. This preliminary action prevents the floating gate potential from being unduly influenced by adjacent cell control gate voltages, thereby maintaining reliability despite reduced floating gate size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces cell-to-cell interference, maintains lower read pass voltages for some unselected word lines, and enhances the reliability of data read and write operations by minimizing the potential difference between adjacent cells, thus addressing the limitations of scaling in memory devices.
Implementation Method 1
electric field strength between word lines and electric field strength between the floating gate of an adjacent cell and a word line become higher
Data Source
AI summary
During data read process, a control circuit gives a read voltage to a selected word line connected to a selected memory cell, and gives read pass voltages, for turning on memory cells, to unselected word lines connected to unselected memory cells. The control circuit respectively gives a first read pass voltage, a second read pass voltage, and a third read pass voltage to a first unselected word line adjacent to the selected word line at a side of at least one of a bit line and a source line, a second unselected word line adjacent to the first unselected word line at a side opposite to the selected word line, and a third unselected word line adjacent to the second unselected word line at a side opposite to the selected word line. The second read pass voltage is higher than the third read pass voltage.