Semiconductor Memory Charge Sharing During Standby
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing power consumption and operational efficiency, particularly in charge sharing operations between memory dies and within memory cell arrays, which affect the performance and longevity of the devices.
Innovation Solution
The semiconductor memory device implements a charge share operation mechanism where electric charge used in read, write, or erase operations is utilized for subsequent operations, reducing the necessary charge amount and operating current, and includes configurations for efficient charge transfer between memory dies, word lines, source lines, and memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If charge sharing operations are performed between memory dies and within memory cell arrays, then operational efficiency is improved, but power consumption and operating current increase
Solution Approach 1:
The patent applies preliminary action by performing charge sharing operations during standby mode before actual read/write/erase operations are needed. The control circuit proactively shares charge between memory dies and within cell arrays during idle periods, so that when operations are required, the charge is already distributed and ready, reducing the peak current demand during active operations.
Solution Approach 2:
The patent implements periodic action by scheduling charge sharing operations to occur at specific intervals during standby mode. The control circuit periodically transfers charge between dies and within arrays rather than continuously, optimizing the balance between maintaining operational readiness and minimizing power consumption during idle periods.
2Use of energy by moving object
If charge sharing operations are performed during standby mode, then power consumption is reduced, but operational readiness may be compromised
Solution Approach 1:
The patent applies feedback by implementing control circuits that monitor the charge states of memory dies and cell arrays, and dynamically adjust charge sharing operations accordingly. The system receives feedback about charge distribution and operational status, then makes real-time decisions about when and how to perform charge sharing, ensuring operational readiness is maintained while optimizing power consumption.
Solution Approach 2:
The patent implements self-service by designing the control circuit to autonomously manage charge sharing operations without external intervention. The control circuit automatically monitors charge states, determines when charge sharing is beneficial, executes the sharing operations, and adjusts based on operational needs, making the system self-regulating and responsive to its own state.
Data Source
AI summary
A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.