Flash Memory Programming Method Compensating Read Margin Reduction

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Solution Overview

Problem

Flash memory devices face challenges in maintaining a sufficient read margin between memory cell states due to electric field coupling and high temperature stress, which widen threshold voltage distributions and reduce the margin between states, making it difficult to determine the programmed state, especially with complex semiconductor fabrication processes.

Innovation Solution

A programming method for flash memory devices that involves a primary program operation to store 2-bit data using target threshold voltages and a secondary program operation to reprogram memory cells within a predetermined threshold voltage region, ensuring a higher threshold voltage and increasing the read margin between states, even when affected by electric field coupling and high temperature stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a small increment of program voltage is used in ISPP scheme to minutely control threshold voltage distributions, then the margin between states is secured, but the programming time increases significantly

Engineering Contradiction:
Improvethreshold voltage distribution control precisionVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent segments the programming operation into two distinct phases: a first programming operation that programs memory cells to initial threshold voltages, and a second programming operation that selectively reprograms specific memory cells to adjust their threshold voltages. This segmentation allows the system to achieve precise threshold voltage control without requiring uniformly small voltage increments across all cells, thereby reducing overall programming time while maintaining state margin security.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary programming of all memory cells to initial threshold voltages in the first programming operation, establishing a baseline state. Then, in the second programming operation, it performs preliminary identification of which specific cells require threshold voltage adjustment based on their coupling characteristics. This preliminary action approach avoids the time-consuming process of applying small voltage increments to all cells uniformly, instead focusing computational and temporal resources only on cells that need adjustment.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If memory cells are programmed with higher threshold voltages to compensate for F-poly coupling, then the read margin is maintained, but the threshold voltage distribution becomes wider

Engineering Contradiction:
Improveread margin between statesVSAvoidthreshold voltage distribution width
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by differentiating the treatment of memory cells based on their specific coupling characteristics. Instead of uniformly increasing threshold voltages for all cells, the system identifies individual cells or groups of cells that experience significant F-poly coupling effects and applies targeted reprogramming only to those specific cells. This localized approach maintains read margins for affected cells without unnecessarily widening the overall threshold voltage distribution across the entire memory array.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent dynamically changes the threshold voltage parameter for specific memory cells based on their coupling characteristics and programming state. The system monitors threshold voltage distributions and selectively adjusts the threshold voltage parameter for individual cells or groups that require compensation, rather than applying a blanket voltage increase to all cells. This selective parameter change maintains sufficient read margins while minimizing the widening of the overall threshold voltage distribution.

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If multiple programming operations are performed to compensate for high temperature stress effects, then the threshold voltage stability is improved, but the programming complexity increases

Engineering Contradiction:
Improvethreshold voltage stability under HTSVSAvoidprogramming operation complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms where the system monitors the threshold voltage distributions and coupling effects resulting from high temperature stress during or after programming operations. Based on this feedback information, the system determines which memory cells require additional reprogramming and adjusts subsequent programming operations accordingly. This feedback-driven approach improves threshold voltage stability under HTS conditions while avoiding unnecessary complexity by only performing additional programming operations when and where needed, rather than applying complex multi-stage programming to all cells uniformly.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7362612B2Program method for flash memory capable of compensating for the reduction of read margin between states
Publication Date: 2008.04.22 SAMSUNG ELECTRONICS CO LTD
  • US7362612B2 patent drawing
  • US7362612B2 patent drawing
  • US7362612B2 patent drawing

AI summary

The invention provides a programming method for a flash memory device including first and second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method may include programming memory cells, connected with a selected row and the second bitlines, with multi-bit data; determining whether the selected row is the last row; and reprogramming programmed memory cells connected with the selected row being the last row and the first bitlines when the determination result is that the selected row is the last row.