Flash Memory Program Method for Read Margin Compensation
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Solution Overview
Problem
Flash memory systems face reduced read margins due to charge loss and electric field coupling, which complicates the control of threshold voltage distributions and makes it difficult to determine the state of programmed memory cells, especially with the increasing complexity of semiconductor fabrication processes.
Innovation Solution
A program method for flash memory devices that involves a primary program operation to store 2-bit data, followed by a secondary program operation to ensure memory cells have threshold voltages equivalent to or higher than predetermined verify voltages, using a series of verify voltages to detect and adjust the programming of memory cells within specific threshold voltage regions, thereby securing a sufficient read margin between states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If increment step pulse programming (ISPP) is used to control threshold voltage distributions, then manufacturing precision of threshold voltage is improved, but programming time increases
Solution Approach 1:
The patent performs preliminary classification of memory cells into different threshold voltage regions before the main programming operation. By pre-identifying cells that need programming and their target regions, the subsequent programming process can be optimized and executed more efficiently, reducing overall programming time while maintaining precise threshold voltage control.
Solution Approach 2:
The patent divides the threshold voltage range into multiple discrete regions and classifies memory cells into these regions based on their initial characteristics. This segmentation allows for region-specific programming strategies, enabling precise control of threshold voltage distributions while optimizing programming time for each group of cells.
2Quantity of substance
If multiple threshold voltage distributions are maintained for multi-bit data storage, then storage capacity is improved, but read margin is reduced due to threshold voltage widening
Solution Approach 1:
The patent applies different verify voltage levels to different threshold voltage regions. By tailoring the verification process to each specific region's characteristics, the system maintains distinct and well-defined threshold voltage distributions for multiple states, ensuring sufficient read margins between states while preserving multi-bit storage capacity.
Solution Approach 2:
The patent dynamically adjusts verify voltage levels based on the threshold voltage region being evaluated. This parameter change strategy ensures that each state's threshold voltage distribution is verified with appropriate voltage levels, maintaining clear separation between states and preserving read margins even as storage capacity increases through multi-bit operations.
3Measurement precision
If threshold voltage distributions are tightly controlled within a determined window, then state discrimination accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the programming and verification process into distinct stages corresponding to different threshold voltage regions. Each stage uses simplified verify voltage levels appropriate for that region, reducing the overall complexity of the programming operation while maintaining high state discrimination accuracy through cumulative regional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively secures a wider read margin between states, even in the presence of electric field coupling and hot temperature stress, by gradually increasing verify voltages to account for charge loss, ensuring accurate state determination and stable threshold voltage distributions.
Implementation Method 1
charges are accumulated in a floating gate (FG) as the memory cell MCB is programmed. When memory cell MCB is programmed, a voltage of floating gate FG of adjacent memory cell MCA rises due to a coupling between floating gates FG of the memory cells MCA and MCB.
Implementation Method 2
HTS means that charges accumulated in a floating gate of a memory cell are drained to a substrate. As the charges of the floating gate are reduced, threshold voltages of memory cells in respective states drop.
Data Source
AI summary
The present invention provides a program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The memory cells are subjected to a primary program operation. Those memory cells arranged within a specific region of respective states are subjected to a secondary program operation to have a threshold voltage equivalent to or higher than a verify voltage used in the primary program operation. Thus, although a threshold voltage distribution is widened due to an electric field coupling/F-poly coupling and HTS, a read margin between adjacent states may be sufficiently secured using the program method.