Latch Balancing Mechanism for Semiconductor Memory Reliability
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Solution Overview
Problem
Semiconductor memory devices face increased data errors due to reduced drive capacity and susceptibility to neutron strikes in fuse latch circuits, leading to higher soft error rates and uncorrectable error correction code errors, which are exacerbated by smaller transistor sizes and lower critical charge requirements.
Innovation Solution
Implementing latch balancing mechanisms, including a driving circuit to control biasing voltage, mirrored latch configurations, and split latch configurations, which enhance the critical charge and N+ area without increasing the transistor size, thereby reducing error rates and increasing robustness against neutron strikes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the transistor size in fuse latch circuits is reduced to decrease device footprint, then the area occupied by the latch is reduced, but the drive capacity and critical charge are lowered, leading to increased soft error rates
Solution Approach 1:
The latch circuit is divided into two separate storage portions (first storage portion and second storage portion) that are distributed at different locations. This segmentation allows the N+ area to be spread out, reducing susceptibility to neutron strikes while maintaining adequate drive capacity. Each portion contributes to the overall critical charge without requiring a single large transistor footprint.
Solution Approach 2:
The patent applies different characteristics to different parts of the latch circuit. The two storage portions are located at different physical positions with different local environments, providing localized charge storage that is more resilient to localized neutron strikes. Each portion can be optimized for its specific location while contributing to the overall latch reliability.
2Volume of moving object
If the transistor size is reduced to minimize device area, then the physical size of the latch is decreased, but the critical charge is reduced, making the latch more susceptible to neutron strikes
Solution Approach 1:
The latch is segmented into two storage portions positioned at different locations. This spatial segmentation ensures that a neutron strike affecting one location does not necessarily affect the other, thereby reducing overall susceptibility to neutron strikes while maintaining compact volume through distributed architecture.
Solution Approach 2:
The patent transitions from a single-location storage approach to a multi-location distributed storage approach. By adding the spatial dimension of distribution, the latch achieves improved neutron strike resistance without proportionally increasing the overall device volume, as the portions are strategically placed rather than simply stacked.
3Area of stationary object
If smaller transistor sizes are used to reduce latch footprint, then the device area is minimized, but the drive capacity is reduced, leading to increased data errors
Solution Approach 1:
The patent combines the charge storage capability of two separate storage portions to achieve the effective drive capacity of a larger latch. By merging the functional contributions of both portions, the circuit maintains adequate drive capacity and critical charge without requiring a single large transistor, thus avoiding data errors while minimizing footprint.
Solution Approach 2:
The latch functionality is segmented across two storage portions, each with smaller transistor sizes that reduce individual footprint. The segmented architecture maintains overall drive capacity by distributing the functional load, preventing data errors that would result from overly small single-transistor latches.
Data Source
AI summary
Methods, apparatuses, and systems related to a memory device are described. The memory device may include local latching circuits each having a retention circuit and a driving circuit. The retention circuit may be configured to provide local storage of broadcasted information for a down-stream circuit. The driving circuit may be configured to connect a first voltage and a second voltage to the retention circuit at different times across the broadcast and the local storage.