Banked Memory Row Degeneration for Fine Granularity
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Solution Overview
Problem
Existing methods for producing memory devices from banked memory architectures result in coarse granularity of row sizes, leading to inefficient designs with increased power consumption and reduced performance, as they constrain row degeneration to be the same across all banks, limiting flexibility and efficiency.
Innovation Solution
A method that allows for the selection of a variable number of memory banks and partitions rows among them, enabling finer granularity and efficient design by not constraining the number of banks to be a factor of the total rows, thereby allowing each bank to have a different number of rows, and optimizing peripheral logic usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If row degeneration is constrained to be the same across all banks, then the design process is simplified, but the granularity of row size control becomes coarse
Solution Approach 1:
The patent divides the memory device into multiple banks, each capable of independent row degeneration. This segmentation allows different row configurations in different banks, enabling fine-grained control over total row count while maintaining manageable design complexity through modular bank-level configuration.
Solution Approach 2:
The patent introduces dynamic row degeneration capability where the number of rows can be independently adjusted in each bank based on design requirements. This dynamic configuration allows the system to adapt row counts flexibly, achieving precise control over memory capacity and performance characteristics.
2Speed
If the number of memory banks is increased, then access speed and power efficiency are improved, but the granularity of row size control becomes coarser
Solution Approach 1:
By segmenting the memory into multiple banks with independent row degeneration, the patent enables fine-grained control over the total number of rows even as the number of banks increases. Each bank can be independently configured to contribute a specific number of rows, allowing precise control over memory capacity and access characteristics.
Solution Approach 2:
The patent applies local quality by allowing different row configurations in different banks based on specific design needs. Each bank can have optimized row counts tailored to local performance requirements, enabling the system to achieve both high access speed through multiple banks and fine-grained row size control through localized configuration.
3Productivity
If custom design is used for particular implementation, then design efficiency is improved, but reusability and cost-effectiveness deteriorate
Solution Approach 1:
The patent creates a universal banked memory architecture that can be configured for different implementations through parameter specification. The same core architecture can produce custom-optimized designs for specific applications while maintaining reusability across different projects, achieving both design efficiency and adaptability through a flexible parameter-driven configuration system.
Solution Approach 2:
The patent enables custom design efficiency through parameter changes by allowing designers to specify desired properties such as row count, bank count, and configuration parameters. The compiler tool uses these parameters to automatically generate optimized instances of the banked memory architecture, providing custom-tailored designs without requiring complete redesigns, thus maintaining both efficiency and reusability.
4Area of stationary object
If peripheral logic is shared between banks, then area efficiency is improved, but flexibility in row configuration is reduced
Solution Approach 1:
The patent segments the memory system into banks with shared peripheral logic, achieving area efficiency through logic reuse. Simultaneously, each bank maintains independent row degeneration capability, providing flexibility in row configuration. This segmentation allows the system to share common infrastructure while enabling customized configurations in each bank.
Solution Approach 2:
The shared peripheral logic serves multiple banks universally, improving area efficiency. The patent enhances this universal approach by allowing each bank to independently configure its row count, making the shared logic adaptable to different row configurations across banks, thus maintaining both area efficiency and configuration flexibility.
Data Source
AI summary
A system, method and computer program product are provided for producing an instance of a memory device from a banked memory architecture. The banked memory architecture specifies a maximum number of memory banks and a maximum number of rows per memory bank. The method comprises the step of receiving input parameters indicating a number of properties of the memory device, the properties comprising at least a number of rows R for the memory device. Thereafter, a degeneration process is performed on the banked memory architecture in order to produce the instance of a memory device having those properties. The degeneration process comprises the steps of: (i) selecting a number of memory banks B for the instance, where the number is an integer less than or equal to the maximum number of memory banks specified by the banked memory architecture, and B is not constrained to be a factor of R; and (ii) partitioning the number of rows R amongst the selected memory banks such that in each memory bank the number of rows in that memory bank is an integer less than or equal to the maximum number of rows per memory bank specified by the banked memory architecture. This has been found to provide a very flexible technique for producing instances from a banked memory architecture allowing fine granularity in the number of rows provided, which is particularly suitable for highly banked memory architectures.