Barrier Modulation Layer for Vertical NAND Memory Window
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Solution Overview
Problem
Existing vertical NAND flash memory devices face challenges in securing a large memory window to achieve multi-level memory storage, which is essential for efficient data retention and programming speed.
Innovation Solution
The semiconductor device incorporates a barrier modulation layer with high electron affinity and low bandgap compared to the tunneling barrier layer and charge trap layer, enhancing the potential barrier for electrons and improving retention characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional tunneling barrier layers and charge trap layers are used in vertical NAND flash memory, then device structure is simple, but memory window is insufficient for multi-level storage
Solution Approach 1:
The barrier modulation layer is divided into multiple sub-layers with different materials and functions: a first sub-layer adjacent to the charge trap layer with high electron affinity to block electrons, and a second sub-layer adjacent to the tunneling barrier layer with low bandgap to facilitate hole injection. This segmentation allows each sub-layer to perform its specific function optimally, achieving multi-level storage capability while managing structural complexity.
Solution Approach 2:
The barrier modulation layer uses composite material structure combining different oxide materials (e.g., TiO2, HfO2, Al2O3) with distinct electronic properties. The first sub-layer uses high electron affinity materials to prevent electron discharge, while the second sub-layer uses low bandgap materials to enable hole injection, creating a composite structure that achieves both electron blocking and hole transport functions simultaneously.
2Reliability
If high electron affinity materials are used in the barrier modulation layer, then electron discharge to gate electrode is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the thickness parameters of each sub-layer to balance manufacturing feasibility and performance. The first sub-layer thickness is controlled at 1-5 nm to provide sufficient electron blocking, while the second sub-layer thickness is controlled at 5-15 nm to enable adequate hole injection. These parameter ranges are selected to achieve reliable retention characteristics while remaining within standard manufacturing tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced potential barrier effectively reduces electron discharge to the gate electrode, thereby improving retention characteristics in the erasing operation state and enhancing the memory device's ability to achieve multi-level memory storage.
Implementation Method 1
The barrier modulation layer is configured to have high electron affinity compared to the tunneling barrier layer and the charge trap layer
Implementation Method 2
The barrier modulation layer is configured to have a low bandgap compared to the tunneling barrier layer and the charge trap layer
Data Source
Figure 1
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Figure 3A~3B
AI summary
Provided are a semiconductor device (100) and a memory device including the same. The semiconductor device includes a channel layer (115), a ferroelectric layer (130) on the channel layer, a charge trap layer (140) on the ferroelectric layer, a barrier modulation layer (150) on the charge trap layer, a tunneling barrier layer (160) on the barrier modulation layer, and a gate electrode (170) on the tunneling barrier layer. The barrier modulation layer is configured to have high electron affinity compared to the tunneling barrier layer and the charge trap layer and to have a low bandgap compared to the tunneling barrier layer and the charge trap layer.