Flash Controller With Batched Execution And Single-Interrupt Completion
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Solution Overview
Problem
Traditional Flash controllers increase CPU overhead and reduce system performance due to frequent interrupts and CPU monitoring of operation status during combined instruction executions.
Innovation Solution
A high-performance Flash controller employs a 'single-configuration-and-multiple-transmission' mechanism with a configuration module and state machine module to execute multiple instructions sequentially, sending a single interrupt signal upon completion, and incorporates a 'post-transmission auto-timing' mechanism to avoid CPU overhead by automatically timing instruction intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional Flash controllers execute multiple instructions sequentially with frequent interrupts, then instruction execution can be completed, but CPU overhead increases and system performance reduces
Solution Approach 1:
The patent applies preliminary action by having the Flash controller internally time the transmission intervals between instructions and automatically generate completion interrupts, so that the CPU does not need to continuously monitor or frequently interrupt to check status. The controller prepares and manages the timing information in advance, allowing batched instruction execution with fewer CPU interventions.
2Reliability
If the CPU continuously monitors operation status, then real-time control is maintained, but CPU overhead increases
Solution Approach 1:
The Flash controller performs self-service by internally timing the transmission intervals and automatically generating completion interrupts without requiring continuous CPU monitoring. The controller manages its own timing and completion signaling, freeing the CPU from continuous status monitoring while maintaining reliable operation control through automated mechanisms.
3Reliability
If frequent interrupts are sent to CPU, then operation completion is notified, but system performance reduces
Solution Approach 1:
The patent merges multiple instruction execution cycles into a single interrupted batch. Instead of sending separate interrupts for each instruction completion, the Flash controller accumulates timing information and sends a single completion interrupt after all instructions are executed, thereby maintaining reliable completion notification while significantly improving system performance by reducing interrupt frequency.
Data Source
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AI summary
The present application relates to a high-performance Flash controller, and an embedded system. The Flash controller comprises a configuration module and a state machine module. The configuration module receives shared configuration information and a plurality of groups of independent configuration information, which correspond to a target operation and are sent by means of a central processing unit, configures each register in a shared register group on the basis of the shared configuration information, and configures each register in each independent register group on the basis of each piece of independent configuration information, wherein the shared configuration information is configuration information that is shared by a plurality of target instructions related to the execution of the target operation, and each group of independent configuration information is configuration information that is independently used for executing each target instruction; and the state machine module controls, on the basis of the shared configuration information and the plurality of groups of independent configuration information, the Flash controller to execute the target instructions in sequence, so as to initiate the target operation to a Flash device, and automatically sends an interrupt signal to the central processing unit by means of the configuration module at the end of the execution of the last target instruction. By using the Flash controller, the overheads of a central processing unit can be reduced, and the system performance can be improved.