Register Arrangements TRIZ Cases
- Physical Register Sharing for Better Register File Utilization
Partitioning large physical registers lets processors hold multiple smaller architected registers, improving availability without added area or power.
- Vector Extract-Merge Instruction for Dependent Beat Processing
Beat-wise status tracking lets dependent vector portions overlap safely, improving code density while limiting instruction overhead.
- VLIW Conditional Execution Slots for Fixed-Length Parallel Instructions
Two auxiliary conditional slots split scalar and vector control, preserving fixed instruction length and parallel execution in VLIW processors.
- Vector Load-Store Buffering for Single LSU Operation Tracking
A buffer decouples vector register micro-ops from one LSU macro-op, reducing backups and improving vector memory throughput.
- Tensor Engine Load-Store Unit for Multi-Dimensional Stride Walking
Dedicated tensor walking and striding hardware removes nested loops and pointer arithmetic to speed multi-dimensional tensor loads and stores.
- Core Load-Store Alignment for Unaligned Memory Data
Alignment circuitry reassembles unaligned data across memory chunks so cores can load registers efficiently with lower area and power.
- Vector Register Aliasing for Low-Latency Data Movement
Alias counters and RAT mapping let vector processors move data without VRF access, cutting latency, power use, and register pressure.
- Complex Multiplication Instruction Format for Vector Processors
A unified vector-friendly instruction format speeds complex multiplication while supporting scalar modes, varied data widths, and memory access.
- Vector Predicate Exposure for Valid Byte Lanes in SIMD Streams
A streaming engine marks valid SIMD byte lanes for partial vectors, cutting loop overhead and improving memory access efficiency.
- Bus-Interleave LUN Control for Address Register Integrity
A pending-status and selective address-latching scheme prevents register corruption during shared-interface multi-LUN operations.
- Near-I/O Pipeline Architecture for Low-Latency AI Memory Access
Direct DRAM access through DMA controllers and a synchronous pipeline loop cuts cache-layer latency and speeds large-model AI data flow.
- SIMD Vector Max/Min Indexing to Cut DSP Sorting Overhead
A SIMD max/min instruction compares register lanes and sets predicate bits to capture value origin while reducing DSP sorting overhead.
- Vector Combining Circuitry for Faster Parallel Register Operations
Specialized decode and combining circuitry speeds repetitive vector register operations while limiting circuit footprint and preserving data precision.
- Point Processor Array Layout for Faster PDE Time-Stepping
Compile-time scheduling and local registers let point processor arrays solve large PDE domains faster with less memory bandwidth.
- Strided 2D Tile Extraction for Faster Matrix Register Packing
Extracts every third element from three 2D arrays into a result tile, reducing instruction-heavy matrix loading and memory scatter overhead.
- Register Renaming With Data Type Prediction for Clustered Register Files
Data type prediction steers logical registers into specialized clusters, cutting register-file energy and delay while preserving hazard handling.
- VLIW Conditional Extension Slots for Fixed-Length Parallel Execution
Two auxiliary conditional instructions split scalar and vector unit control, preserving fixed VLIW packet length while reducing extra cycles.
- FPGA Data Migration via Avalon-MM to Avalon-ST Decoupling
A protocol conversion chip separates burst-read control from FPGA algorithms by bridging Avalon-MM memory access to Avalon-ST data streaming.