VLIW Conditional Execution Slots for Fixed-Length Parallel Instructions
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Solution Overview
Problem
In VLIW processors, conditional instruction execution faces challenges due to the need for additional bits to specify multiple registers, which reduces opcode space and can exceed instruction length, especially when parallel functional units are involved.
Innovation Solution
The solution involves employing two conditional execution auxiliary instructions for disparate subsets of functional units and splitting the functional units into scalar and vector sets with separate register files, limiting simultaneous access and optimizing register usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If more registers are available to control conditional execution, then conditional execution capability is improved, but more bits are needed within each instruction which reduces opcode space
Solution Approach 1:
The patent segments the conditional execution control into two separate auxiliary instructions: one for scalar functional units and one for vector functional units. Each auxiliary instruction contains condition register bits specific to its target subset, thereby distributing the bit requirements across multiple instructions rather than requiring all condition bits in a single instruction format.
2Adaptability or versatility
If bits are added to specify conditional operation for all functional units, then conditional execution control is improved, but the instruction length exceeds fixed length which complicates coding/decoding
Solution Approach 1:
The patent divides functional units into two distinct subsets (scalar and vector) and creates separate auxiliary instructions for each subset. This segmentation ensures that each instruction remains within the fixed length constraint while providing comprehensive conditional execution control across all functional units through the combined use of both auxiliary instructions.
3Ease of operation
If functional units are divided into separate sets with corresponding register files, then access control is improved, but the number of functional units that may simultaneously access register files is limited
Solution Approach 1:
The patent implements a shared scalar data register file that can be accessed by both scalar functional units and vector functional units. This multi-functional register file design allows different functional unit sets to access the same register resources, thereby maintaining ease of operation through unified access control while preserving simultaneous access capability across diverse functional units.
Data Source
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AI summary
In described examples, a very long instruction word (VLIW) data processor includes functional units operable to perform a predetermined execute packet of instructions in parallel. An instruction directed to a functional unit may be made conditional via one of two conditional execution auxiliary instructions in the same execute packet. Each conditional execution auxiliary instruction includes a first field identifying the instruction (1408) and fields including conditional bits for corresponding functional units (1401, 1402, 1403, 1404, 1405, 1406). The two conditional execution auxiliary instructions include condition register identification bits for disparate subsets of functional units. For each functional unit operation, if the execute packet includes a corresponding conditional execution auxiliary instruction, then operation is conditional upon the status of the identified register. The condition bits preferably include an additional zero bit determining whether the condition is upon the identified register being zero or non-zero.