Bus-Interleave LUN Control for Address Register Integrity
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Solution Overview
Problem
Address register corruption occurs in multiple logic unit (LUN) operations due to shared memory interfaces, leading to inefficiencies and reliability issues when one LUN receives commands intended for another.
Innovation Solution
Implementing a pending status for the first LUN to ignore non-multi-plane program operation commands and using an address entry and counter to selectively enable latching of addresses, ensuring the address register only stores valid addresses during multi-plane operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple LUNs share a memory interface to improve productivity, then device complexity is reduced, but address register corruption occurs reducing reliability
Solution Approach 1:
The system performs preliminary actions by setting a pending status flag before executing multi-plane program operations. This preliminary status indication prevents the LUN from accepting interruptible operations (like read commands) that would cause address register corruption, while still allowing the shared memory interface to be used efficiently for multiple LUN operations.
Solution Approach 2:
The patent introduces an intermediary mechanism (the pending status flag and corresponding control logic) between the shared memory interface and the address register. This intermediary prevents direct conflicts by mediating what operations can be accepted during multi-plane program operations, thereby eliminating address register corruption while maintaining interface sharing.
2Ease of operation
If the first LUN accepts all operations via shared memory interface, then ease of operation is improved, but address register becomes corrupted
Solution Approach 1:
The system implements feedback by using the pending status flag to communicate the current operational state of the first LUN to the controller. This feedback mechanism allows the controller to understand when the first LUN should not accept interruptible operations, preventing address register corruption while maintaining simple command reception through the shared interface.
Solution Approach 2:
The system sets a preliminary pending status before executing multi-plane program operations, which preemptively prevents the LUN from accepting operations that would corrupt the address register. This preliminary action maintains ease of operation while ensuring reliability.
3Reliability
If the first LUN enters pending status to prevent address corruption, then reliability is improved, but operational complexity increases
Solution Approach 1:
The patent extracts the critical control function into a separate, dedicated mechanism (the pending status flag and associated control logic). This extraction isolates the complexity management to a specific module, preventing address register corruption while containing the operational complexity within a well-defined control structure rather than dispersing it throughout the entire system.
Solution Approach 2:
The pending status flag acts as an intermediary control element that simplifies the overall system architecture by providing a clear state indication. This intermediary mechanism manages the complexity of coordinating multiple LUN operations on a shared interface without requiring complex real-time arbitration logic.
Data Source
AI summary
A memory device includes a first logic unit (LUN) and a second LUN. The first LUN is coupled to the second LUN and configured to receive a first multi-plane operation command of a set of multi-plane operation commands corresponding to the first LUN, latch a first address of the first multi-plane operation command into a first address register of the first LUN, receive a single-plane operation command that includes a second address and corresponds to the second LUN, and keep latching the first address into the first address register.