Vector Predicate Exposure for Valid Byte Lanes in SIMD Streams
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern digital signal processors face challenges with increasing workloads, memory bandwidth limitations, memory system latency, and unreliable memories, which impact real-time data processing and memory access efficiency, particularly in systems on a chip (SOC) with complex algorithms.
Innovation Solution
A digital data processor with a streaming engine that fetches a predetermined sequence of data elements from memory for use in vector processing units, handling variable data lengths by packing data in lanes and using a scalar predicate register for conditional operations, and a streaming engine that manages memory access and address generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is packed in lanes of defined width in vector stream head register, then memory access efficiency is improved, but device complexity increases
Solution Approach 1:
The data stream is segmented into multiple lanes within the vector stream head register, with each lane capable of holding a portion of the data. This segmentation allows parallel processing of multiple data elements simultaneously, improving memory access efficiency while managing complexity through structured organization
Solution Approach 2:
The patent introduces a new dimension for data organization by packing data elements in lanes of defined width within the vector stream head register. This multi-dimensional data structure (lanes × elements) enables more efficient memory access patterns compared to traditional scalar or simple vector approaches
2Reliability
If streaming engine produces scalar valid data for each lane, then reliability is improved, but device complexity increases
Solution Approach 1:
The streaming engine pre-computes and produces scalar valid data indicators for each lane before the actual data processing occurs. This preliminary action ensures that validity information is readily available when needed, improving reliability without requiring complex runtime validation logic
Solution Approach 2:
The scalar valid data acts as an intermediary between the vector stream head register and the functional units. This intermediary provides explicit validity information that mediates the data flow, ensuring reliable processing while keeping the overall system architecture manageable
3Productivity
If not all lanes include valid data at end of stream, then productivity is maintained, but reliability deteriorates
Solution Approach 1:
The system processes partial data in the final vector by using only the valid lanes and ignoring the excess lanes that don't contain valid data. This partial action approach maintains high throughput by continuing processing rather than waiting for complete data, while the valid data indicators ensure reliability by preventing processing of invalid data portions
4Ease of operation
If stream valid data is automatically written to predetermined data register, then ease of operation is improved, but device complexity increases
Solution Approach 1:
The streaming engine automatically writes the scalar valid data to a predetermined data register without requiring explicit programmer intervention or complex control logic. This self-service mechanism simplifies operation by handling the validity data transfer autonomously, while the automated nature prevents the complexity that would arise from manual management
Data Source
AI summary
A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.