FPGA Data Migration via Avalon-MM to Avalon-ST Decoupling
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Solution Overview
Problem
Existing FPGA data migration systems face challenges with complex protocol conversion and data flow scheduling between FPGA storage and acceleration algorithm cores, leading to high coupling, poor generality, and difficulties in development, maintenance, and portability.
Innovation Solution
A data migration method that decouples control of data reading from the algorithm module by using a preset protocol conversion module to convert Avalon-MM bus protocol to Avalon-ST bus protocol, involving a controller to calculate burst addresses and lengths, and a packetizer to transfer data to an FPGA algorithm module.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If protocol conversion and data flow scheduling are integrated into the algorithm module, then data migration functionality is achieved, but device complexity and coupling increase
Solution Approach 1:
The patent divides the data migration system into separate functional modules: the algorithm module focuses on computation tasks, while a dedicated data migration module handles protocol conversion and data flow scheduling. This segmentation allows each module to specialize in its core function, reducing coupling and improving maintainability while achieving comprehensive data migration capability.
Solution Approach 2:
The patent introduces a standard bus interface as an intermediary between the algorithm module and the data migration module. This standard interface decouples the modules by providing a well-defined communication protocol, allowing them to interact without direct dependency, thus reducing coupling while maintaining full functionality.
2Productivity
If custom protocol conversion is implemented within the algorithm module, then data migration is achieved, but ease of manufacture and portability deteriorate
Solution Approach 1:
The patent implements a universal data migration module that can handle multiple protocols and data formats through standardized interfaces. This module serves multiple purposes: protocol conversion, data flow scheduling, and interface standardization, making the system more manufacturable and portable while maintaining full data migration functionality.
Solution Approach 2:
By introducing a standard bus interface as an intermediary, the patent enables the algorithm module to remain generic and portable while the data migration module handles protocol-specific implementations. This separation makes the system easier to manufacture and maintain as each module can be developed and tested independently.
3Productivity
If the algorithm module handles both computation and data reading control, then complete data processing is achieved, but ease of operation worsens
Solution Approach 1:
The patent segments the responsibilities by assigning computation tasks to the algorithm module and data reading control to a dedicated data migration module. This clear division allows the algorithm module to focus purely on computation, improving its usability and ease of operation, while the complete data processing functionality is maintained through the coordinated work of both modules.
Solution Approach 2:
The data migration module autonomously handles data reading control, protocol conversion, and flow scheduling without requiring the algorithm module to manage these operations. This self-service capability simplifies the algorithm module's interface and improves ease of operation while maintaining complete data processing through the migration module's automated handling.
Data Source
AI summary
Provided is a data migration method, including: setting a read data length and an initial read address of a first bus to a read data length register and a read address register in a preset protocol conversion chip; calculating, by a controller in the preset protocol conversion chip, a burst read address and a burst length of each burst on the first bus based on the initial read address and the read data length, transferring the burst read address and the burst length to a first bus slave chip, causing the first bus slave chip to read data in a memory and return the data to the preset protocol conversion chip; placing, by a packetizer in the preset protocol conversion chip, the data onto a second bus, and providing the data to a FPGA algorithm chip through the second bus.